* device/lib/pic/libdev/devices.txt: device list for mkall.sh

[fw/sdcc] / device / lib / pic / libdev / pic16f84a.c

diff --git a/device/lib/pic/libdev/pic16f84a.c b/device/lib/pic/libdev/pic16f84a.c
index 184499c0ca8f305b6619707cdf10282b951e636c..d96e900856af6dd3f425e689bf7e0f10f087f2d3 100644 (file)
--- a/device/lib/pic/libdev/pic16f84a.c
+++ b/device/lib/pic/libdev/pic16f84a.c
@@ -1,26 +1,26 @@
 /* Register definitions for pic16f84a.
  * This file was automatically generated by:
- *   inc2h.pl V1.6
+ *   inc2h.pl V4514
  *   Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
  */
 #include <pic16f84a.h>
 
-data __at (INDF_ADDR) volatile char      INDF;
-sfr  __at (TMR0_ADDR)                    TMR0;
-data __at (PCL_ADDR) volatile char       PCL;
-sfr  __at (STATUS_ADDR)                  STATUS;
-sfr  __at (FSR_ADDR)                     FSR;
-sfr  __at (PORTA_ADDR)                   PORTA;
-sfr  __at (PORTB_ADDR)                   PORTB;
-sfr  __at (EEDATA_ADDR)                  EEDATA;
-sfr  __at (EEADR_ADDR)                   EEADR;
-sfr  __at (PCLATH_ADDR)                  PCLATH;
-sfr  __at (INTCON_ADDR)                  INTCON;
-sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
-sfr  __at (TRISA_ADDR)                   TRISA;
-sfr  __at (TRISB_ADDR)                   TRISB;
-sfr  __at (EECON1_ADDR)                  EECON1;
-sfr  __at (EECON2_ADDR)                  EECON2;
+__data __at (INDF_ADDR) volatile char      INDF;
+__sfr  __at (TMR0_ADDR)                    TMR0;
+__data __at (PCL_ADDR) volatile char       PCL;
+__sfr  __at (STATUS_ADDR)                  STATUS;
+__sfr  __at (FSR_ADDR)                     FSR;
+__sfr  __at (PORTA_ADDR)                   PORTA;
+__sfr  __at (PORTB_ADDR)                   PORTB;
+__sfr  __at (EEDATA_ADDR)                  EEDATA;
+__sfr  __at (EEADR_ADDR)                   EEADR;
+__sfr  __at (PCLATH_ADDR)                  PCLATH;
+__sfr  __at (INTCON_ADDR)                  INTCON;
+__sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
+__sfr  __at (TRISA_ADDR)                   TRISA;
+__sfr  __at (TRISB_ADDR)                   TRISB;
+__sfr  __at (EECON1_ADDR)                  EECON1;
+__sfr  __at (EECON2_ADDR)                  EECON2;
 
 // 
 // bitfield definitions
@@ -28,5 +28,9 @@ sfr  __at (EECON2_ADDR)                  EECON2;
 volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
 volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
 volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
+volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
 volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
+volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;