* .version: bumped version to 2.5.6 (pic14 ABI changed)

[fw/sdcc] / device / lib / pic / libdev / pic16f685.c

diff --git a/device/lib/pic/libdev/pic16f685.c b/device/lib/pic/libdev/pic16f685.c
new file mode 100644 (file)
index 0000000..1218104
--- /dev/null
+++ b/device/lib/pic/libdev/pic16f685.c
@@ -0,0 +1,94 @@
+/* Register definitions for pic16f685.
+ * This file was automatically generated by:
+ *   inc2h.pl V1.6
+ *   Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+ */
+#include <pic16f685.h>
+
+data __at (INDF_ADDR) volatile char      INDF;
+sfr  __at (TMR0_ADDR)                    TMR0;
+data __at (PCL_ADDR) volatile char       PCL;
+sfr  __at (STATUS_ADDR)                  STATUS;
+sfr  __at (FSR_ADDR)                     FSR;
+sfr  __at (PORTA_ADDR)                   PORTA;
+sfr  __at (PORTB_ADDR)                   PORTB;
+sfr  __at (PORTC_ADDR)                   PORTC;
+sfr  __at (PCLATH_ADDR)                  PCLATH;
+sfr  __at (INTCON_ADDR)                  INTCON;
+sfr  __at (PIR1_ADDR)                    PIR1;
+sfr  __at (PIR2_ADDR)                    PIR2;
+sfr  __at (TMR1L_ADDR)                   TMR1L;
+sfr  __at (TMR1H_ADDR)                   TMR1H;
+sfr  __at (T1CON_ADDR)                   T1CON;
+sfr  __at (TMR2_ADDR)                    TMR2;
+sfr  __at (T2CON_ADDR)                   T2CON;
+sfr  __at (CCPR1L_ADDR)                  CCPR1L;
+sfr  __at (CCPR1H_ADDR)                  CCPR1H;
+sfr  __at (CCP1CON_ADDR)                 CCP1CON;
+sfr  __at (PWM1CON_ADDR)                 PWM1CON;
+sfr  __at (ECCPAS_ADDR)                  ECCPAS;
+sfr  __at (ADRESH_ADDR)                  ADRESH;
+sfr  __at (ADCON0_ADDR)                  ADCON0;
+sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
+sfr  __at (TRISA_ADDR)                   TRISA;
+sfr  __at (TRISB_ADDR)                   TRISB;
+sfr  __at (TRISC_ADDR)                   TRISC;
+sfr  __at (PIE1_ADDR)                    PIE1;
+sfr  __at (PIE2_ADDR)                    PIE2;
+sfr  __at (PCON_ADDR)                    PCON;
+sfr  __at (OSCCON_ADDR)                  OSCCON;
+sfr  __at (OSCTUNE_ADDR)                 OSCTUNE;
+sfr  __at (PR2_ADDR)                     PR2;
+sfr  __at (WPU_ADDR)                     WPU;
+sfr  __at (WPUA_ADDR)                    WPUA;
+sfr  __at (IOC_ADDR)                     IOC;
+sfr  __at (IOCA_ADDR)                    IOCA;
+sfr  __at (WDTCON_ADDR)                  WDTCON;
+sfr  __at (ADRESL_ADDR)                  ADRESL;
+sfr  __at (ADCON1_ADDR)                  ADCON1;
+sfr  __at (EEDATA_ADDR)                  EEDATA;
+sfr  __at (EEADR_ADDR)                   EEADR;
+sfr  __at (EEDATH_ADDR)                  EEDATH;
+sfr  __at (EEADRH_ADDR)                  EEADRH;
+sfr  __at (WPUB_ADDR)                    WPUB;
+sfr  __at (IOCB_ADDR)                    IOCB;
+sfr  __at (VRCON_ADDR)                   VRCON;
+sfr  __at (CM1CON0_ADDR)                 CM1CON0;
+sfr  __at (CM2CON0_ADDR)                 CM2CON0;
+sfr  __at (CM2CON1_ADDR)                 CM2CON1;
+sfr  __at (ANSEL_ADDR)                   ANSEL;
+sfr  __at (ANSELH_ADDR)                  ANSELH;
+sfr  __at (EECON1_ADDR)                  EECON1;
+sfr  __at (EECON2_ADDR)                  EECON2;
+sfr  __at (PSTRCON_ADDR)                 PSTRCON;
+sfr  __at (SRCON_ADDR)                   SRCON;
+
+// 
+// bitfield definitions
+// 
+volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
+volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
+volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
+volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
+volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
+volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
+volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
+volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
+volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
+volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
+volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
+volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
+volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
+volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
+volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
+volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
+volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
+volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
+