* device/lib/pic/libdev/Makefile.in: build device-specific

[fw/sdcc] / device / lib / pic / libdev / pic12f683.c

diff --git a/device/lib/pic/libdev/pic12f683.c b/device/lib/pic/libdev/pic12f683.c
index a23fd02f331d12a933b78526d0953131f9a180f5..a62112d1d15569fab9bdcd03ec1465f27fc2db81 100644 (file)
--- a/device/lib/pic/libdev/pic12f683.c
+++ b/device/lib/pic/libdev/pic12f683.c
@@ -1,13 +1,13 @@
 /* Register definitions for pic12f683.
  * This file was automatically generated by:
- *   inc2h.pl V1.7
+ *   inc2h.pl V4585
  *   Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
  */
 #include <pic12f683.h>
 
-__data __at (INDF_ADDR) volatile char      INDF;
+__sfr  __at (INDF_ADDR)                    INDF;
 __sfr  __at (TMR0_ADDR)                    TMR0;
-__data __at (PCL_ADDR) volatile char       PCL;
+__sfr  __at (PCL_ADDR)                     PCL;
 __sfr  __at (STATUS_ADDR)                  STATUS;
 __sfr  __at (FSR_ADDR)                     FSR;
 __sfr  __at (GPIO_ADDR)                    GPIO;
@@ -51,10 +51,15 @@ __sfr  __at (ANSEL_ADDR)                   ANSEL;
 // bitfield definitions
 // 
 volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
+volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
 volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
 volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
 volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
+volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
+volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
 volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
+volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
 volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
 volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
 volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;