* device/lib/pic/libdev/Makefile.in: build device-specific

[fw/sdcc] / device / lib / hc08 / _divuint.c

diff --git a/device/lib/hc08/_divuint.c b/device/lib/hc08/_divuint.c
index f6c34b299ecdc6b379529205b286fee3424d4ca0..c8a8add59da580632fe77bb173938aa2010217c6 100644 (file)
--- a/device/lib/hc08/_divuint.c
+++ b/device/lib/hc08/_divuint.c
@@ -44,101 +44,101 @@
 static void
 _divuint_dummy (void) _naked
 {
-       _asm
+  __asm
 
-               .globl __divuint
+    .globl __divuint
 
-       __divuint:
+  __divuint:
 
-               #define count   r2
-               #define reste_l r3
-               #define reste_h r4
-               #define al      dpl
-               #define ah      dph
+    #define count   r2
+    #define reste_l r3
+    #define reste_h r4
+    #define al      dpl
+    #define ah      dph
 
 #if defined(SDCC_STACK_AUTO) && !defined(SDCC_PARMS_IN_BANK1)
 
-               ar0 = 0                 ; BUG register set is not considered
-               ar1 = 1
+    ar0 = 0     ; BUG register set is not considered
+    ar1 = 1
 
-               .globl __divint
+    .globl __divint
 
-               mov     a,sp
-               add     a,#-2           ; 2 bytes return address
-               mov     r0,a            ; r0 points to bh
-               mov     ar1,@r0         ; load bh
-               dec     r0
-               mov     ar0,@r0         ; load bl
+    mov a,sp
+    add a,#-2   ; 2 bytes return address
+    mov r0,a    ; r0 points to bh
+    mov ar1,@r0   ; load bh
+    dec r0
+    mov ar0,@r0   ; load bl
 
-               #define bl      r0
-               #define bh      r1
+    #define bl      r0
+    #define bh      r1
 
-       __divint:                       ; entry point for __divsint
+  __divint:     ; entry point for __divsint
 
 
 #else // SDCC_STACK_AUTO
 
 #if !defined(SDCC_PARMS_IN_BANK1)
 #if defined(SDCC_NOOVERLAY)
-               .area DSEG    (DATA)
+    .area DSEG    (DATA)
 #else
-               .area OSEG    (OVR,DATA)
+    .area OSEG    (OVR,DATA)
 #endif
 
-               .globl __divuint_PARM_2
-               .globl __divsint_PARM_2
+    .globl __divuint_PARM_2
+    .globl __divsint_PARM_2
 
-       __divuint_PARM_2:
-       __divsint_PARM_2:
-               .ds     2
+  __divuint_PARM_2:
+  __divsint_PARM_2:
+    .ds 2
 
-               .area CSEG    (CODE)
+    .area CSEG    (CODE)
 #endif // !SDCC_PARMS_IN_BANK1
 #if defined(SDCC_PARMS_IN_BANK1)
-               #define bl      (b1_0)
-               #define bh      (b1_1)
+    #define bl      (b1_0)
+    #define bh      (b1_1)
 #else
-               #define bl      (__divuint_PARM_2)
-               #define bh      (__divuint_PARM_2 + 1)
+    #define bl      (__divuint_PARM_2)
+    #define bh      (__divuint_PARM_2 + 1)
 #endif // SDCC_PARMS_IN_BANK1
 #endif // SDCC_STACK_AUTO
 
-               mov     count,#16
-               clr     a
-               mov     reste_l,a
-               mov     reste_h,a
-
-       loop:   mov     a,al            ; a <<= 1
-               add     a,acc
-               mov     al,a
-               mov     a,ah
-               rlc     a
-               mov     ah,a
-
-               mov     a,reste_l       ; reste <<= 1
-               rlc     a               ;   feed in carry
-               mov     reste_l,a
-               mov     a,reste_h
-               rlc     a
-               mov     reste_h,a
-
-               mov     a,reste_l       ; reste - b
-               subb    a,bl            ; here carry is always clear, because
-                                       ; reste <<= 1 never overflows
-               mov     b,a
-               mov     a,reste_h
-               subb    a,bh
-
-               jc      smaller         ; reste >= b?
-
-               mov     reste_h,a       ; -> yes;  reste = reste - b;
-               mov     reste_l,b
-               orl     al,#1
-       smaller:                        ; -> no
-               djnz    count,loop
-               ret
-
-       _endasm ;
+    mov count,#16
+    clr a
+    mov reste_l,a
+    mov reste_h,a
+
+  loop: mov a,al    ; a <<= 1
+    add a,acc
+    mov al,a
+    mov a,ah
+    rlc a
+    mov ah,a
+
+    mov a,reste_l ; reste <<= 1
+    rlc a   ;   feed in carry
+    mov reste_l,a
+    mov a,reste_h
+    rlc a
+    mov reste_h,a
+
+    mov a,reste_l ; reste - b
+    subb  a,bl    ; here carry is always clear, because
+          ; reste <<= 1 never overflows
+    mov b,a
+    mov a,reste_h
+    subb  a,bh
+
+    jc  smaller   ; reste >= b?
+
+    mov reste_h,a ; -> yes;  reste = reste - b;
+    mov reste_l,b
+    orl al,#1
+  smaller:      ; -> no
+    djnz  count,loop
+    ret
+
+  __endasm ;
 }
 
 #else  // defined _DIVUINT_ASM_SMALL || defined _DIVUINT_ASM_SMALL_AUTO