/* Special Function Registers */
-sfr at 0x80 P0 ; // Port 0
-sfr at 0x81 SP ; // Stack Pointer
-sfr at 0x82 DPL ; // Data Pointer Low
-sfr at 0x83 DPH ; // Data Pointer High
-sfr at 0x84 P0M1 ; // Port 0 output mode 1
-sfr at 0x85 P0M2 ; // Port 0 output mode 2
-sfr at 0x86 KBI ; // Keyboard interrupt
-sfr at 0x87 PCON ; // Power Control
-sfr at 0x88 TCON ; // Timer Control
-sfr at 0x89 TMOD ; // Timer Mode
-sfr at 0x8A TL0 ; // Timer Low 0
-sfr at 0x8B TL1 ; // Timer Low 1
-sfr at 0x8C TH0 ; // Timer High 0
-sfr at 0x8D TH1 ; // Timer High 1
-
-sfr at 0x90 P1 ; // Port 1
-sfr at 0x91 P1M1 ; // Port 1 output mode 1
-sfr at 0x92 P1M2 ; // Port 1 output mode 2
-sfr at 0x95 DIVM ; // CPU clock divide by N control
-sfr at 0x98 SCON ; // Serial Control
-sfr at 0x99 SBUF ; // Serial Data Buffer
-
-sfr at 0xA0 P2 ; // Port 2
-sfr at 0xA2 AUXR1 ; // Auxilliary 1 (not available on 80C51FA/87C51Fx)
-sfr at 0xA4 P2M1 ; // Port 2 output mode 1
-sfr at 0xA5 P2M2 ; // Port 2 output mode 2
-sfr at 0xA6 WDRST ; // Watchdog reset register
-sfr at 0xA7 WDCON ; // Watchdog control register
-sfr at 0xA8 IEN0 ; // Interrupt Enable 0
-sfr at 0xA9 SADDR ; // Serial slave Address
-sfr at 0xAC CMP1 ; // Comparator 1 control register
-sfr at 0xAD CMP2 ; // Comparator 2 control register
-
-sfr at 0xB7 IP0H ; // Interrupt Priority 0 High
-sfr at 0xB8 IP0 ; // Interrupt Priority 0
-sfr at 0xB9 SADEN ; // Serial slave Address Mask
-
-sfr at 0xC8 I2CFG ; // I2C configuration register
-
-sfr at 0xD0 PSW ; // Program Status Word
-sfr at 0xD8 I2CON ; // I2C control register
-sfr at 0xD9 I2DAT ; // I2C data register
-
-sfr at 0xE0 ACC ; // Accumulator
-sfr at 0xE8 IEN1 ; // Interrupt enable 1
-
-sfr at 0xF0 B ; // B Register
-sfr at 0xF6 PT0AD ; // Port 0 digital input disable
-sfr at 0xF7 IP1H ; // Interrupt Priority 1 High
-sfr at 0xF8 IP1 ; // Interrupt Priority 1
+__sfr __at 0x80 P0 ; // Port 0
+__sfr __at 0x81 SP ; // Stack Pointer
+__sfr __at 0x82 DPL ; // Data Pointer Low
+__sfr __at 0x83 DPH ; // Data Pointer High
+__sfr __at 0x84 P0M1 ; // Port 0 output mode 1
+__sfr __at 0x85 P0M2 ; // Port 0 output mode 2
+__sfr __at 0x86 KBI ; // Keyboard interrupt
+__sfr __at 0x87 PCON ; // Power Control
+__sfr __at 0x88 TCON ; // Timer Control
+__sfr __at 0x89 TMOD ; // Timer Mode
+__sfr __at 0x8A TL0 ; // Timer Low 0
+__sfr __at 0x8B TL1 ; // Timer Low 1
+__sfr __at 0x8C TH0 ; // Timer High 0
+__sfr __at 0x8D TH1 ; // Timer High 1
+
+__sfr __at 0x90 P1 ; // Port 1
+__sfr __at 0x91 P1M1 ; // Port 1 output mode 1
+__sfr __at 0x92 P1M2 ; // Port 1 output mode 2
+__sfr __at 0x95 DIVM ; // CPU clock divide by N control
+__sfr __at 0x98 SCON ; // Serial Control
+__sfr __at 0x99 SBUF ; // Serial Data Buffer
+
+__sfr __at 0xA0 P2 ; // Port 2
+__sfr __at 0xA2 AUXR1 ; // Auxilliary 1 (not available on 80C51FA/87C51Fx)
+__sfr __at 0xA4 P2M1 ; // Port 2 output mode 1
+__sfr __at 0xA5 P2M2 ; // Port 2 output mode 2
+__sfr __at 0xA6 WDRST ; // Watchdog reset register
+__sfr __at 0xA7 WDCON ; // Watchdog control register
+__sfr __at 0xA8 IEN0 ; // Interrupt Enable 0
+__sfr __at 0xA9 SADDR ; // Serial slave Address
+__sfr __at 0xAC CMP1 ; // Comparator 1 control register
+__sfr __at 0xAD CMP2 ; // Comparator 2 control register
+
+__sfr __at 0xB7 IP0H ; // Interrupt Priority 0 High
+__sfr __at 0xB8 IP0 ; // Interrupt Priority 0
+__sfr __at 0xB9 SADEN ; // Serial slave Address Mask
+
+__sfr __at 0xC8 I2CFG ; // I2C configuration register
+
+__sfr __at 0xD0 PSW ; // Program Status Word
+__sfr __at 0xD8 I2CON ; // I2C control register
+__sfr __at 0xD9 I2DAT ; // I2C data register
+
+__sfr __at 0xE0 ACC ; // Accumulator
+__sfr __at 0xE8 IEN1 ; // Interrupt enable 1
+
+__sfr __at 0xF0 B ; // B Register
+__sfr __at 0xF6 PT0AD ; // Port 0 digital input disable
+__sfr __at 0xF7 IP1H ; // Interrupt Priority 1 High
+__sfr __at 0xF8 IP1 ; // Interrupt Priority 1
/* Bit Addressable Registers */
/* P0 */
-sbit at 0x80 P0_0 ; // Also CMP2
-sbit at 0x81 P0_1 ; // Also CIN2B
-sbit at 0x82 P0_2 ; // Also CIN2A
-sbit at 0x83 P0_3 ; // Also CIN1B
-sbit at 0x84 P0_4 ; // Also CIN1A
-sbit at 0x85 P0_5 ; // Also CMPREF
-sbit at 0x86 P0_6 ; // Also CMP1
-sbit at 0x87 P0_7 ; // Also T1
+__sbit __at 0x80 P0_0 ; // Also CMP2
+__sbit __at 0x81 P0_1 ; // Also CIN2B
+__sbit __at 0x82 P0_2 ; // Also CIN2A
+__sbit __at 0x83 P0_3 ; // Also CIN1B
+__sbit __at 0x84 P0_4 ; // Also CIN1A
+__sbit __at 0x85 P0_5 ; // Also CMPREF
+__sbit __at 0x86 P0_6 ; // Also CMP1
+__sbit __at 0x87 P0_7 ; // Also T1
/* TCON */
-sbit at 0x88 IT0 ; // External Interrupt 0 Type
-sbit at 0x89 IE0 ; // External Interrupt 0 Edge Flag
-sbit at 0x8A IT1 ; // External Interrupt 1 Type
-sbit at 0x8B IE1 ; // External Interrupt 1 Edge Flag
-sbit at 0x8C TR0 ; // Timer 0 Run Control
-sbit at 0x8D TF0 ; // Timer 0 Overflow Flag
-sbit at 0x8E TR1 ; // Timer 1 Run Control
-sbit at 0x8F TF1 ; // Timer 1 Overflow Flag
+__sbit __at 0x88 IT0 ; // External Interrupt 0 Type
+__sbit __at 0x89 IE0 ; // External Interrupt 0 Edge Flag
+__sbit __at 0x8A IT1 ; // External Interrupt 1 Type
+__sbit __at 0x8B IE1 ; // External Interrupt 1 Edge Flag
+__sbit __at 0x8C TR0 ; // Timer 0 Run Control
+__sbit __at 0x8D TF0 ; // Timer 0 Overflow Flag
+__sbit __at 0x8E TR1 ; // Timer 1 Run Control
+__sbit __at 0x8F TF1 ; // Timer 1 Overflow Flag
/* P1 */
-sbit at 0x90 P1_0 ; // Also TxD
-sbit at 0x91 P1_1 ; // Also RxD
-sbit at 0x92 P1_2 ; // Also T0
-sbit at 0x93 P1_3 ; // Also INT0
-sbit at 0x94 P1_4 ; // Also INT1
-sbit at 0x95 P1_5 ; // Also RST
-sbit at 0x96 P1_6 ;
-sbit at 0x97 P1_7 ;
+__sbit __at 0x90 P1_0 ; // Also TxD
+__sbit __at 0x91 P1_1 ; // Also RxD
+__sbit __at 0x92 P1_2 ; // Also T0
+__sbit __at 0x93 P1_3 ; // Also INT0
+__sbit __at 0x94 P1_4 ; // Also INT1
+__sbit __at 0x95 P1_5 ; // Also RST
+__sbit __at 0x96 P1_6 ;
+__sbit __at 0x97 P1_7 ;
/* SCON */
-sbit at 0x98 RI ; // Receive Interrupt Flag
-sbit at 0x99 TI ; // Transmit Interrupt Flag
-sbit at 0x9A RB8 ; // Receive Bit 8
-sbit at 0x9B TB8 ; // Transmit Bit 8
-sbit at 0x9C REN ; // Receiver Enable
-sbit at 0x9D SM2 ; // Serial Mode Control Bit 2
-sbit at 0x9E SM1 ; // Serial Mode Control Bit 1
-sbit at 0x9F SM0 ; // Serial Mode Control Bit 0
+__sbit __at 0x98 RI ; // Receive Interrupt Flag
+__sbit __at 0x99 TI ; // Transmit Interrupt Flag
+__sbit __at 0x9A RB8 ; // Receive Bit 8
+__sbit __at 0x9B TB8 ; // Transmit Bit 8
+__sbit __at 0x9C REN ; // Receiver Enable
+__sbit __at 0x9D SM2 ; // Serial Mode Control Bit 2
+__sbit __at 0x9E SM1 ; // Serial Mode Control Bit 1
+__sbit __at 0x9F SM0 ; // Serial Mode Control Bit 0
/* P2 */
-sbit at 0xA0 P2_0 ; // Also X2
-sbit at 0xA1 P2_1 ; // Also X1
+__sbit __at 0xA0 P2_0 ; // Also X2
+__sbit __at 0xA1 P2_1 ; // Also X1
/* IEN0 */
-sbit at 0xA8 EX0 ; // External Interrupt 0 Enable
-sbit at 0xA9 ET0 ; // Timer 0 Interrupt Enable
-sbit at 0xAA EX1 ; // External Interrupt 1 Enable
-sbit at 0xAB ET1 ; // Timer 1 Interrupt Enable
-sbit at 0xAC ES ; // Serial Port Interrupt Enable
-sbit at 0xAD EBO ; // Brownout Interrupt Enable
-sbit at 0xAE EWD ; // Watchdog Interrupt Enable
-sbit at 0xAF EA ; // Global Interrupt Enable
+__sbit __at 0xA8 EX0 ; // External Interrupt 0 Enable
+__sbit __at 0xA9 ET0 ; // Timer 0 Interrupt Enable
+__sbit __at 0xAA EX1 ; // External Interrupt 1 Enable
+__sbit __at 0xAB ET1 ; // Timer 1 Interrupt Enable
+__sbit __at 0xAC ES ; // Serial Port Interrupt Enable
+__sbit __at 0xAD EBO ; // Brownout Interrupt Enable
+__sbit __at 0xAE EWD ; // Watchdog Interrupt Enable
+__sbit __at 0xAF EA ; // Global Interrupt Enable
/* IP0 */
-sbit at 0xB8 PX0 ; // External Interrupt 0 Priority
-sbit at 0xB9 PT0 ; // Timer 0 Interrupt Priority
-sbit at 0xBA PX1 ; // External Interrupt 1 Priority
-sbit at 0xBB PT1 ; // Timer 1 Interrupt Priority
-sbit at 0xBC PS ; // Serial Port Interrupt Priority
-sbit at 0xBD PB0 ; // Brownout Interrupt Priority
-sbit at 0xBE PWD ; // Watchdog Interrupt Priority
+__sbit __at 0xB8 PX0 ; // External Interrupt 0 Priority
+__sbit __at 0xB9 PT0 ; // Timer 0 Interrupt Priority
+__sbit __at 0xBA PX1 ; // External Interrupt 1 Priority
+__sbit __at 0xBB PT1 ; // Timer 1 Interrupt Priority
+__sbit __at 0xBC PS ; // Serial Port Interrupt Priority
+__sbit __at 0xBD PB0 ; // Brownout Interrupt Priority
+__sbit __at 0xBE PWD ; // Watchdog Interrupt Priority
/* I2CFG */
-sbit at 0xC8 CT0 ; // Clock Time Select 0
-sbit at 0xC9 CT1 ; // Clock Time Select 1
-sbit at 0xCC TIRUN ; // Timer I Run Enable
-sbit at 0xCD CLRTI ; // Clear Timer I
-sbit at 0xCE MASTRQ; // Master Request
-sbit at 0xCF SLAVEN; // Slave Enable
+__sbit __at 0xC8 CT0 ; // Clock Time Select 0
+__sbit __at 0xC9 CT1 ; // Clock Time Select 1
+__sbit __at 0xCC TIRUN ; // Timer I Run Enable
+__sbit __at 0xCD CLRTI ; // Clear Timer I
+__sbit __at 0xCE MASTRQ; // Master Request
+__sbit __at 0xCF SLAVEN; // Slave Enable
/* PSW */
-sbit at 0xD0 P ; // Accumulator Parity Flag
-sbit at 0xD1 F1 ; // Flag 1
-sbit at 0xD2 OV ; // Overflow Flag
-sbit at 0xD3 RS0 ; // Register Bank Select 0
-sbit at 0xD4 RS1 ; // Register Bank Select 1
-sbit at 0xD5 F0 ; // Flag 0
-sbit at 0xD6 AC ; // Auxiliary Carry Flag
-sbit at 0xD7 CY ; // Carry Flag
+__sbit __at 0xD0 P ; // Accumulator Parity Flag
+__sbit __at 0xD1 F1 ; // Flag 1
+__sbit __at 0xD2 OV ; // Overflow Flag
+__sbit __at 0xD3 RS0 ; // Register Bank Select 0
+__sbit __at 0xD4 RS1 ; // Register Bank Select 1
+__sbit __at 0xD5 F0 ; // Flag 0
+__sbit __at 0xD6 AC ; // Auxiliary Carry Flag
+__sbit __at 0xD7 CY ; // Carry Flag
/* I2CON */
-sbit at 0xD8 XSTP ;
-sbit at 0xD9 MASTER;// Master Status
-sbit at 0xDA STP ; // Stop Detect Flag
-sbit at 0xDB STR ; // Start Detect Flag
-sbit at 0xDC ARL ; // Arbitration Loss Flag
-sbit at 0xDD DRDY ; // Data Ready Flag
-sbit at 0xDE ATN ; // Attention: I2C Interrupt Flag
-sbit at 0xDF RDAT ; // I2C Read Data
+__sbit __at 0xD8 XSTP ;
+__sbit __at 0xD9 MASTER;// Master Status
+__sbit __at 0xDA STP ; // Stop Detect Flag
+__sbit __at 0xDB STR ; // Start Detect Flag
+__sbit __at 0xDC ARL ; // Arbitration Loss Flag
+__sbit __at 0xDD DRDY ; // Data Ready Flag
+__sbit __at 0xDE ATN ; // Attention: I2C Interrupt Flag
+__sbit __at 0xDF RDAT ; // I2C Read Data
/* ACC */
-sbit at 0xE0 ACC_0;
-sbit at 0xE1 ACC_1;
-sbit at 0xE2 ACC_2;
-sbit at 0xE3 ACC_3;
-sbit at 0xE4 ACC_4;
-sbit at 0xE5 ACC_5;
-sbit at 0xE6 ACC_6;
-sbit at 0xE7 ACC_7;
+__sbit __at 0xE0 ACC_0;
+__sbit __at 0xE1 ACC_1;
+__sbit __at 0xE2 ACC_2;
+__sbit __at 0xE3 ACC_3;
+__sbit __at 0xE4 ACC_4;
+__sbit __at 0xE5 ACC_5;
+__sbit __at 0xE6 ACC_6;
+__sbit __at 0xE7 ACC_7;
/* IEN1 */
-sbit at 0xE8 EI2 ; // I2C Interrupt Enable
-sbit at 0xE9 EKB ; // Keyboard Interrupt Enable
-sbit at 0xEA EC2 ; // Comparator 2 Interrupt Enable
-sbit at 0xED EC1 ; // Comparator 1 Interrupt Enable
-sbit at 0xEF ETI ; // Timer I Interrupt Enable
+__sbit __at 0xE8 EI2 ; // I2C Interrupt Enable
+__sbit __at 0xE9 EKB ; // Keyboard Interrupt Enable
+__sbit __at 0xEA EC2 ; // Comparator 2 Interrupt Enable
+__sbit __at 0xED EC1 ; // Comparator 1 Interrupt Enable
+__sbit __at 0xEF ETI ; // Timer I Interrupt Enable
/* B */
-sbit at 0xF0 B_0;
-sbit at 0xF1 B_1;
-sbit at 0xF2 B_2;
-sbit at 0xF3 B_3;
-sbit at 0xF4 B_4;
-sbit at 0xF5 B_5;
-sbit at 0xF6 B_6;
-sbit at 0xF7 B_7;
+__sbit __at 0xF0 B_0;
+__sbit __at 0xF1 B_1;
+__sbit __at 0xF2 B_2;
+__sbit __at 0xF3 B_3;
+__sbit __at 0xF4 B_4;
+__sbit __at 0xF5 B_5;
+__sbit __at 0xF6 B_6;
+__sbit __at 0xF7 B_7;
/* IP1 */
-sbit at 0xF8 PI2; // I2C Interrupt Priority
-sbit at 0xF9 PKB; // Keyboard Interrupt Priority
-sbit at 0xFA PC2; // Comparator 2 Interrupt Priority
-sbit at 0xFD PC1; // Comparator 1 Interrupt Priority
-sbit at 0xFF PTI; // Timer I Interrupt Priority
+__sbit __at 0xF8 PI2; // I2C Interrupt Priority
+__sbit __at 0xF9 PKB; // Keyboard Interrupt Priority
+__sbit __at 0xFA PC2; // Comparator 2 Interrupt Priority
+__sbit __at 0xFD PC1; // Comparator 1 Interrupt Priority
+__sbit __at 0xFF PTI; // Timer I Interrupt Priority
/* Bitmasks for SFRs */
projects / fw / sdcc / blobdiff