/* Configuration registers locations */
-#define __CONFIG0H 0x300001
-#define __CONFIG1L 0x300002
-#define __CONFIG1H 0x300003
-#define __CONFIG2H 0x300005
-#define __CONFIG3L 0x300006
-#define __CONFIG4L 0x300008
-#define __CONFIG4H 0x300009
-#define __CONFIG5L 0x30000A
-#define __CONFIG5H 0x30000B
-#define __CONFIG6L 0x30000C
-#define __CONFIG6H 0x30000D
-
-
-
-/* Oscillator 0H options */
-#define _OSC_11XX_0H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
-#define _OSC_101X_0H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
-#define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_0H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */
-#define _OSC_INT_Port_on_RA6_Port_on_RA7_0H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */
-#define _OSC_EXT_Port_on_RA6_0H 0xF7 /* EXT RC-Port_on_RA6 */
-#define _OSC_HS_PLL_0H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
-#define _OSC_EC_PORT_0H 0xF5 /* EC-Port on RA6 */
-#define _OSC_EC_CLKOUT_0H 0xF4 /* EC-CLKOUT on RA6 */
-#define _OSC_EXT_CLKOUT_on_RA6_0H 0xF3 /* EXT RC-CLKOUT_on_RA6 */
-#define _OSC_HS_0H 0xF2 /* HS */
-#define _OSC_XT_0H 0xF1 /* XT */
-#define _OSC_LP_0H 0xF0 /* LP */
-
-/* Fail Safe Clock Monitor Enable 0H options */
-#define _FCMEN_OFF_0H 0xBF /* Disabled */
-#define _FCMEN_ON_0H 0xFF /* Enabled */
-
-/* Internal External Switch Over 0H options */
-#define _IESO_OFF_0H 0x7F /* Disabled */
-#define _IESO_ON_0H 0xFF /* Enabled */
-
-/* Power Up Timer 1L options */
-#define _PUT_OFF_1L 0xFF /* Disabled */
-#define _PUT_ON_1L 0xFE /* Enabled */
-
-/* Brown Out Detect 1L options */
-#define _BODEN_ON_1L 0xFF /* Enabled */
-#define _BODEN_OFF_1L 0xFD /* Disabled */
-
-/* Brown Out Voltage 1L options */
-#define _BODENV_2_0V_1L 0xFF /* 2.0V */
-#define _BODENV_2_7V_1L 0xFB /* 2.7V */
-#define _BODENV_4_2V_1L 0xF7 /* 4.2V */
-#define _BODENV_4_5V_1L 0xF3 /* 4.5V */
-
-/* Watchdog Timer 1H options */
-#define _WDT_ON_1H 0xFF /* Enabled */
-#define _WDT_DISABLED_CONTROLLED_1H 0xFE /* Disabled-Controlled by SWDTEN bit */
-
-/* Watchdog Postscaler 1H options */
-#define _WDTPS_1_32768_1H 0xFF /* 1:32768 */
-#define _WDTPS_1_16384_1H 0xFD /* 1:16384 */
-#define _WDTPS_1_8192_1H 0xFB /* 1:8192 */
-#define _WDTPS_1_4096_1H 0xF9 /* 1:4096 */
-#define _WDTPS_1_2048_1H 0xF7 /* 1:2048 */
-#define _WDTPS_1_1024_1H 0xF5 /* 1:1024 */
-#define _WDTPS_1_512_1H 0xF3 /* 1:512 */
-#define _WDTPS_1_256_1H 0xF1 /* 1:256 */
-#define _WDTPS_1_128_1H 0xEF /* 1:128 */
-#define _WDTPS_1_64_1H 0xED /* 1:64 */
-#define _WDTPS_1_32_1H 0xEB /* 1:32 */
-#define _WDTPS_1_16_1H 0xE9 /* 1:16 */
-#define _WDTPS_1_8_1H 0xE7 /* 1:8 */
-#define _WDTPS_1_4_1H 0xE5 /* 1:4 */
-#define _WDTPS_1_2_1H 0xE3 /* 1:2 */
-#define _WDTPS_1_1_1H 0xE1 /* 1:1 */
-
-/* MCLR enable 2H options */
-#define _MCLRE_MCLR_enabled_RA5_input_dis_2H 0xFF /* MCLR enabled__RA5_input_disabled */
-#define _MCLRE_MCLR_disabled_RA5_input_en_2H 0x7F /* MCLR disabled__RA5_input_enabled */
-
-/* Stack Overflow Reset 3L options */
-#define _STVR_ON_3L 0xFF /* Enabled */
-#define _STVR_OFF_3L 0xFE /* Disabled */
-
-/* Low Voltage Program 3L options */
-#define _LVP_ON_3L 0xFF /* Enabled */
-#define _LVP_OFF_3L 0xFB /* Disabled */
-
-/* Background Debug 3L options */
-#define _BACKBUG_OFF_3L 0xFF /* Disabled */
-#define _BACKBUG_ON_3L 0x7F /* Enabled */
-
-/* Code Protect 000200-0007FF 4L options */
-#define _CP_0_OFF_4L 0xFF /* Disabled */
-#define _CP_0_ON_4L 0xFE /* Enabled */
-
-/* Code Protect 000800-000FFF 4L options */
-#define _CP_1_OFF_4L 0xFF /* Disabled */
-#define _CP_1_ON_4L 0xFD /* Enabled */
-
-/* Data EE Read Protect 4H options */
-#define _CPD_OFF_4H 0xFF /* Disabled */
-#define _CPD_ON_4H 0x7F /* Enabled */
-
-/* Code Protect Boot 4H options */
-#define _CPB_OFF_4H 0xFF /* Disabled */
-#define _CPB_ON_4H 0xBF /* Enabled */
-
-/* Table Write Protect 00200-007FF 5L options */
-#define _WRT_0_OFF_5L 0xFF /* Disabled */
-#define _WRT_0_ON_5L 0xFE /* Enabled */
-
-/* Table Write Protect 00800-00FFF 5L options */
-#define _WRT_1_OFF_5L 0xFF /* Disabled */
-#define _WRT_1_ON_5L 0xFD /* Enabled */
-
-/* Data EE Write Protect 5H options */
-#define _WRTD_OFF_5H 0xFF /* Disabled */
-#define _WRTD_ON_5H 0x7F /* Enabled */
-
-/* Table Write Protect Boot 5H options */
-#define _WRTB_OFF_5H 0xFF /* Disabled */
-#define _WRTB_ON_5H 0xBF /* Enabled */
-
-/* Config. Write Protect 5H options */
-#define _WRTC_OFF_5H 0xFF /* Disabled */
-#define _WRTC_ON_5H 0xDF /* Enabled */
-
-/* Table Read Protect 00200-007FF 6L options */
-#define _EBTR_0_OFF_6L 0xFF /* Disabled */
-#define _EBTR_0_ON_6L 0xFE /* Enabled */
-
-/* Table Read Protect 000800-00FFF 6L options */
-#define _EBTR_1_OFF_6L 0xFF /* Disabled */
-#define _EBTR_1_ON_6L 0xFD /* Enabled */
-
-/* Table Read Protect Boot 6H options */
-#define _EBTRB_OFF_6H 0xFF /* Disabled */
-#define _EBTRB_ON_6H 0xBF /* Enabled */
+#define __CONFIG1H 0x300001
+#define __CONFIG2L 0x300002
+#define __CONFIG2H 0x300003
+#define __CONFIG3H 0x300005
+#define __CONFIG4L 0x300006
+#define __CONFIG5L 0x300008
+#define __CONFIG5H 0x300009
+#define __CONFIG6L 0x30000A
+#define __CONFIG6H 0x30000B
+#define __CONFIG7L 0x30000C
+#define __CONFIG7H 0x30000D
+
+
+
+/* Oscillator 1H options */
+#define _OSC_11XX_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
+#define _OSC_101X_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
+#define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_1H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */
+#define _OSC_INT_Port_on_RA6_Port_on_RA7_1H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */
+#define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */
+#define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
+#define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */
+#define _OSC_EC_CLKOUT_1H 0xF4 /* EC-CLKOUT on RA6 */
+#define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */
+#define _OSC_HS_1H 0xF2 /* HS */
+#define _OSC_XT_1H 0xF1 /* XT */
+#define _OSC_LP_1H 0xF0 /* LP */
+
+/* Fail Safe Clock Monitor Enable 1H options */
+#define _FCMEN_OFF_1H 0xBF /* Disabled */
+#define _FCMEN_ON_1H 0xFF /* Enabled */
+
+/* Internal External Switch Over 1H options */
+#define _IESO_OFF_1H 0x7F /* Disabled */
+#define _IESO_ON_1H 0xFF /* Enabled */
+
+/* Power Up Timer 2L options */
+#define _PUT_OFF_2L 0xFF /* Disabled */
+#define _PUT_ON_2L 0xFE /* Enabled */
+
+/* Brown Out Detect 2L options */
+#define _BODEN_ON_2L 0xFF /* Enabled */
+#define _BODEN_OFF_2L 0xFD /* Disabled */
+
+/* Brown Out Voltage 2L options */
+#define _BODENV_2_0V_2L 0xFF /* 2.0V */
+#define _BODENV_2_7V_2L 0xFB /* 2.7V */
+#define _BODENV_4_2V_2L 0xF7 /* 4.2V */
+#define _BODENV_4_5V_2L 0xF3 /* 4.5V */
+
+/* Watchdog Timer 2H options */
+#define _WDT_ON_2H 0xFF /* Enabled */
+#define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
+
+/* Watchdog Postscaler 2H options */
+#define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
+#define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
+#define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
+#define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
+#define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
+#define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
+#define _WDTPS_1_512_2H 0xF3 /* 1:512 */
+#define _WDTPS_1_256_2H 0xF1 /* 1:256 */
+#define _WDTPS_1_128_2H 0xEF /* 1:128 */
+#define _WDTPS_1_64_2H 0xED /* 1:64 */
+#define _WDTPS_1_32_2H 0xEB /* 1:32 */
+#define _WDTPS_1_16_2H 0xE9 /* 1:16 */
+#define _WDTPS_1_8_2H 0xE7 /* 1:8 */
+#define _WDTPS_1_4_2H 0xE5 /* 1:4 */
+#define _WDTPS_1_2_2H 0xE3 /* 1:2 */
+#define _WDTPS_1_1_2H 0xE1 /* 1:1 */
+
+/* MCLR enable 3H options */
+#define _MCLRE_MCLR_enabled_RA5_input_dis_3H 0xFF /* MCLR enabled__RA5_input_disabled */
+#define _MCLRE_MCLR_disabled_RA5_input_en_3H 0x7F /* MCLR disabled__RA5_input_enabled */
+
+/* Stack Overflow Reset 4L options */
+#define _STVR_ON_4L 0xFF /* Enabled */
+#define _STVR_OFF_4L 0xFE /* Disabled */
+
+/* Low Voltage Program 4L options */
+#define _LVP_ON_4L 0xFF /* Enabled */
+#define _LVP_OFF_4L 0xFB /* Disabled */
+
+/* Background Debug 4L options */
+#define _BACKBUG_OFF_4L 0xFF /* Disabled */
+#define _BACKBUG_ON_4L 0x7F /* Enabled */
+
+/* Code Protect 000200-0007FF 5L options */
+#define _CP_0_OFF_5L 0xFF /* Disabled */
+#define _CP_0_ON_5L 0xFE /* Enabled */
+
+/* Code Protect 000800-000FFF 5L options */
+#define _CP_1_OFF_5L 0xFF /* Disabled */
+#define _CP_1_ON_5L 0xFD /* Enabled */
+
+/* Data EE Read Protect 5H options */
+#define _CPD_OFF_5H 0xFF /* Disabled */
+#define _CPD_ON_5H 0x7F /* Enabled */
+
+/* Code Protect Boot 5H options */
+#define _CPB_OFF_5H 0xFF /* Disabled */
+#define _CPB_ON_5H 0xBF /* Enabled */
+
+/* Table Write Protect 00200-007FF 6L options */
+#define _WRT_0_OFF_6L 0xFF /* Disabled */
+#define _WRT_0_ON_6L 0xFE /* Enabled */
+
+/* Table Write Protect 00800-00FFF 6L options */
+#define _WRT_1_OFF_6L 0xFF /* Disabled */
+#define _WRT_1_ON_6L 0xFD /* Enabled */
+
+/* Data EE Write Protect 6H options */
+#define _WRTD_OFF_6H 0xFF /* Disabled */
+#define _WRTD_ON_6H 0x7F /* Enabled */
+
+/* Table Write Protect Boot 6H options */
+#define _WRTB_OFF_6H 0xFF /* Disabled */
+#define _WRTB_ON_6H 0xBF /* Enabled */
+
+/* Config. Write Protect 6H options */
+#define _WRTC_OFF_6H 0xFF /* Disabled */
+#define _WRTC_ON_6H 0xDF /* Enabled */
+
+/* Table Read Protect 00200-007FF 7L options */
+#define _EBTR_0_OFF_7L 0xFF /* Disabled */
+#define _EBTR_0_ON_7L 0xFE /* Enabled */
+
+/* Table Read Protect 000800-00FFF 7L options */
+#define _EBTR_1_OFF_7L 0xFF /* Disabled */
+#define _EBTR_1_ON_7L 0xFD /* Enabled */
+
+/* Table Read Protect Boot 7H options */
+#define _EBTRB_OFF_7H 0xFF /* Disabled */
+#define _EBTRB_ON_7H 0xBF /* Enabled */
/* Device ID locations */
projects / fw / sdcc / blobdiff