* device/lib/pic/libdev/devices.txt: device list for mkall.sh

[fw/sdcc] / device / include / pic / pic12f675.h

diff --git a/device/include/pic/pic12f675.h b/device/include/pic/pic12f675.h
index b12101bdf9415125f9f40f683889bb3eb76df82f..e2519dd755bb09c3135a6a5887b467f45c97a19f 100644 (file)
--- a/device/include/pic/pic12f675.h
+++ b/device/include/pic/pic12f675.h
@@ -4,7 +4,7 @@
 //
 // This header file was automatically generated by:
 //
-//     inc2h.pl V1.7
+//     inc2h.pl V4514
 //
 //     Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
 //
@@ -172,7 +172,7 @@ extern __sfr  __at (ANSEL_ADDR)                   ANSEL;
 //----- T1CON Bits ---------------------------------------------------------
 
 
-//----- CMCON Bits --------------------------------------------------------
+//----- COMCON Bits --------------------------------------------------------
 
 
 //----- ADCON0 Bits --------------------------------------------------------
@@ -288,6 +288,29 @@ extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
 #define VCFG                 ADCON0_bits.VCFG
 #define ADFM                 ADCON0_bits.ADFM
 
+// ----- ANSEL bits --------------------
+typedef union {
+  struct {
+    unsigned char ANS0:1;
+    unsigned char ANS1:1;
+    unsigned char ANS2:1;
+    unsigned char ANS3:1;
+    unsigned char ADCS0:1;
+    unsigned char ADCS1:1;
+    unsigned char ADCS2:1;
+    unsigned char :1;
+  };
+} __ANSEL_bits_t;
+extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
+
+#define ANS0                 ANSEL_bits.ANS0
+#define ANS1                 ANSEL_bits.ANS1
+#define ANS2                 ANSEL_bits.ANS2
+#define ANS3                 ANSEL_bits.ANS3
+#define ADCS0                ANSEL_bits.ADCS0
+#define ADCS1                ANSEL_bits.ADCS1
+#define ADCS2                ANSEL_bits.ADCS2
+
 // ----- CMCON bits --------------------
 typedef union {
   struct {
@@ -310,6 +333,26 @@ extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
 #define CINV                 CMCON_bits.CINV
 #define COUT                 CMCON_bits.COUT
 
+// ----- EECON1 bits --------------------
+typedef union {
+  struct {
+    unsigned char RD:1;
+    unsigned char WR:1;
+    unsigned char WREN:1;
+    unsigned char WRERR:1;
+    unsigned char :1;
+    unsigned char :1;
+    unsigned char :1;
+    unsigned char :1;
+  };
+} __EECON1_bits_t;
+extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
+
+#define RD                   EECON1_bits.RD
+#define WR                   EECON1_bits.WR
+#define WREN                 EECON1_bits.WREN
+#define WRERR                EECON1_bits.WRERR
+
 // ----- GPIO bits --------------------
 typedef union {
   struct {
@@ -596,50 +639,19 @@ typedef union {
     unsigned char VR1:1;
     unsigned char VR2:1;
     unsigned char VR3:1;
-    unsigned char ADCS0:1;
-    unsigned char VRR:1;
-    unsigned char ADCS2:1;
-    unsigned char VREN:1;
-  };
-  struct {
-    unsigned char RD:1;
-    unsigned char WR:1;
-    unsigned char WREN:1;
-    unsigned char WRERR:1;
-    unsigned char :1;
-    unsigned char ADCS1:1;
-    unsigned char :1;
-    unsigned char :1;
-  };
-  struct {
-    unsigned char ANS0:1;
-    unsigned char ANS1:1;
-    unsigned char ANS2:1;
-    unsigned char ANS3:1;
-    unsigned char :1;
-    unsigned char :1;
     unsigned char :1;
+    unsigned char VRR:1;
     unsigned char :1;
+    unsigned char VREN:1;
   };
 } __VRCON_bits_t;
 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
 
 #define VR0                  VRCON_bits.VR0
-#define RD                   VRCON_bits.RD
-#define ANS0                 VRCON_bits.ANS0
 #define VR1                  VRCON_bits.VR1
-#define WR                   VRCON_bits.WR
-#define ANS1                 VRCON_bits.ANS1
 #define VR2                  VRCON_bits.VR2
-#define WREN                 VRCON_bits.WREN
-#define ANS2                 VRCON_bits.ANS2
 #define VR3                  VRCON_bits.VR3
-#define WRERR                VRCON_bits.WRERR
-#define ANS3                 VRCON_bits.ANS3
-#define ADCS0                VRCON_bits.ADCS0
 #define VRR                  VRCON_bits.VRR
-#define ADCS1                VRCON_bits.ADCS1
-#define ADCS2                VRCON_bits.ADCS2
 #define VREN                 VRCON_bits.VREN
 
 #endif