\r
// SFR Registers and BITs\r
\r
-SFR(P0, 0x80) // Port 0\r
+SFR(P0, 0x80); // Port 0\r
SBIT(P0_0, 0x80, 0); // Port 0 bit 0\r
SBIT(P0_1, 0x80, 1); // Port 0 bit 1\r
SBIT(P0_2, 0x80, 2); // Port 0 bit 2\r
SBIT(P0_5, 0x80, 5); // Port 0 bit 5\r
SBIT(P0_6, 0x80, 6); // Port 0 bit 6\r
SBIT(P0_7, 0x80, 7); // Port 0 bit 7\r
-SFR(SP, 0x81) // Stack Pointer\r
-SFR(DPL0, 0x82) // Data Pointer 0 Low Byte\r
-SFR(DPH0, 0x83) // Data Pointer 0 High Byte\r
-SFR(DPL1, 0x84) // Data Pointer 1 Low Byte\r
-SFR(DPH1, 0x85) // Data Pointer 1 High Byte\r
-SFR(U0CSR, 0x86) // USART 0 Control and Status\r
-SFR(PCON, 0x87) // Power Mode Control\r
-SFR(TCON, 0x88) // Interrupt Flags\r
+SFR(SP, 0x81); // Stack Pointer\r
+SFR(DPL0, 0x82); // Data Pointer 0 Low Byte\r
+SFR(DPH0, 0x83); // Data Pointer 0 High Byte\r
+SFR(DPL1, 0x84); // Data Pointer 1 Low Byte\r
+SFR(DPH1, 0x85); // Data Pointer 1 High Byte\r
+SFR(U0CSR, 0x86); // USART 0 Control and Status\r
+SFR(PCON, 0x87); // Power Mode Control\r
+SFR(TCON, 0x88); // Interrupt Flags\r
SBIT(IT0, 0x88, 0); // reserved (must always be set to 1)\r
SBIT(RFERRIF, 0x88, 1); // RFERR \96 RF TX/RX FIFO interrupt flag\r
SBIT(IT1, 0x88, 2); // reserved (must always be set to 1)\r
SBIT(URX0IF, 0x88, 3); // USART0 RX Interrupt Flag\r
SBIT(ADCIF, 0x88, 5); // ADC Interrupt Flag\r
SBIT(URX1IF, 0x88, 7); // USART1 RX Interrupt Flag\r
-SFR(P0IFG, 0x89) // Port 0 Interrupt Status Flag\r
-SFR(P1IFG, 0x8A) // Port 1 Interrupt Status Flag\r
-SFR(P2IFG, 0x8B) // Port 2 Interrupt Status Flag\r
-SFR(PICTL, 0x8C) // Port Interrupt Control\r
-SFR(P1IEN, 0x8D) // Port 1 Interrupt Mask\r
-SFR(P0INP, 0x8F) // Port 0 Input Mode\r
-SFR(P1, 0x90) // Port 1\r
+SFR(P0IFG, 0x89); // Port 0 Interrupt Status Flag\r
+SFR(P1IFG, 0x8A); // Port 1 Interrupt Status Flag\r
+SFR(P2IFG, 0x8B); // Port 2 Interrupt Status Flag\r
+SFR(PICTL, 0x8C); // Port Interrupt Control\r
+SFR(P1IEN, 0x8D); // Port 1 Interrupt Mask\r
+SFR(P0INP, 0x8F); // Port 0 Input Mode\r
+SFR(P1, 0x90); // Port 1\r
SBIT(P1_0, 0x90, 0); // Port 1 bit 0\r
SBIT(P1_1, 0x90, 1); // Port 1 bit 1\r
SBIT(P1_2, 0x90, 2); // Port 1 bit 2\r
SBIT(P1_5, 0x90, 5); // Port 1 bit 5\r
SBIT(P1_6, 0x90, 6); // Port 1 bit 6\r
SBIT(P1_7, 0x90, 7); // Port 1 bit 7\r
-SFR(RFIM, 0x91) // RF Interrupt Mask\r
-SFR(DPS, 0x92) // Data Pointer Select\r
-SFR(MPAGE, 0x93) // Memory Page Select\r
-SFR(_XPAGE, 0x93) // Memory Page Select under the name SDCC needs it\r
-SFR(T2CMP, 0x94) // Timer 2 Compare Value\r
-SFR(ST0, 0x95) // Sleep Timer 0\r
-SFR(ST1, 0x96) // Sleep Timer 1\r
-SFR(ST2, 0x97) // Sleep Timer 2\r
-SFR(S0CON, 0x98) // Interrupt Flags 2\r
+SFR(RFIM, 0x91); // RF Interrupt Mask\r
+SFR(DPS, 0x92); // Data Pointer Select\r
+SFR(MPAGE, 0x93); // Memory Page Select\r
+SFR(_XPAGE, 0x93); // Memory Page Select under the name SDCC needs it\r
+SFR(T2CMP, 0x94); // Timer 2 Compare Value\r
+SFR(ST0, 0x95); // Sleep Timer 0\r
+SFR(ST1, 0x96); // Sleep Timer 1\r
+SFR(ST2, 0x97); // Sleep Timer 2\r
+SFR(S0CON, 0x98); // Interrupt Flags 2\r
SBIT(ENCIF_0, 0x98, 0); // AES Interrupt Flag 0\r
SBIT(ENCIF_1, 0x98, 1); // AES Interrupt Flag 1\r
-SFR(IEN2, 0x9A) // Interrupt Enable 2\r
-SFR(S1CON, 0x9B) // Interrupt Flags 3\r
-SFR(T2PEROF0, 0x9C) // Timer 2 Overflow Capture/Compare 0\r
-SFR(T2PEROF1, 0x9D) // Timer 2 Overflow Capture/Compare 1\r
-SFR(T2PEROF2, 0x9E) // Timer 2 Overflow Capture/Compare 2\r
-SFR(P2, 0xA0) // Port 2\r
+SFR(IEN2, 0x9A); // Interrupt Enable 2\r
+SFR(S1CON, 0x9B); // Interrupt Flags 3\r
+SFR(T2PEROF0, 0x9C); // Timer 2 Overflow Capture/Compare 0\r
+SFR(T2PEROF1, 0x9D); // Timer 2 Overflow Capture/Compare 1\r
+SFR(T2PEROF2, 0x9E); // Timer 2 Overflow Capture/Compare 2\r
+SFR(P2, 0xA0); // Port 2\r
SBIT(P2_0, 0xA0, 0); // Port 2 bit 0\r
SBIT(P2_1, 0xA0, 1); // Port 2 bit 1\r
SBIT(P2_2, 0xA0, 2); // Port 2 bit 2\r
SBIT(P2_5, 0xA0, 5); // Port 2 bit 5\r
SBIT(P2_6, 0xA0, 6); // Port 2 bit 6\r
SBIT(P2_7, 0xA0, 7); // Port 2 bit 7\r
-SSFR(T2OF0, 0xA1) // Timer 2 Overflow Count 0\r
-SFR(T2OF1, 0xA2) // Timer 2 Overflow Count 1\r
-SFR(T2OF2, 0xA3) // Timer 2 Overflow Count 2\r
-SFR(T2CAPLPL, 0xA4) // Timer 2 Period Low Byte\r
-SFR(T2CAPHPH, 0xA5) // Timer 2 Period High Byte\r
-SFR(T2TLD, 0xA6) // Timer 2 Timer Value Low Byte\r
-SFR(T2THD, 0xA7) // Timer 2 Timer Value High Byte\r
-SFR(IEN0, 0xA8) // Interrupt Enable 0\r
+SFR(T2OF0, 0xA1); // Timer 2 Overflow Count 0\r
+SFR(T2OF1, 0xA2); // Timer 2 Overflow Count 1\r
+SFR(T2OF2, 0xA3); // Timer 2 Overflow Count 2\r
+SFR(T2CAPLPL, 0xA4); // Timer 2 Period Low Byte\r
+SFR(T2CAPHPH, 0xA5); // Timer 2 Period High Byte\r
+SFR(T2TLD, 0xA6); // Timer 2 Timer Value Low Byte\r
+SFR(T2THD, 0xA7); // Timer 2 Timer Value High Byte\r
+SFR(IEN0, 0xA8); // Interrupt Enable 0\r
SBIT(RFERRIE, 0xA8, 0); // RF TX/RX FIFO interrupt enable\r
SBIT(ADCIE, 0xA8, 1); // ADC Interrupt Enable\r
SBIT(URX0IE, 0xA8, 2); // USART0 RX Interrupt Enable\r
SBIT(ENCIE, 0xA8, 4); // AES Encryption/Decryption Interrupt Enable\r
SBIT(STIE, 0xA8, 5); // Sleep Timer Interrupt Enable\r
SBIT(EA, 0xA8, 7); // Global Interrupt Enable\r
-SFR(IP0, 0xA9) // Interrupt Priority 0\r
-SFR(FWT, 0xAB) // Flash Write Timing\r
-SFR(FADDRL, 0xAC) // Flash Address Low Byte\r
-SFR(FADDRH, 0xAD) // Flash Address High Byte\r
-SFR(FCTL, 0xAE) // Flash Control\r
-SFR(FWDATA, 0xAF) // Flash Write Data\r
-SFR(ENCDI, 0xB1) // Encryption Input Data\r
-SFR(ENCDO, 0xB2) // Encryption Output Data\r
-SFR(ENCCS, 0xB3) // Encryption Control and Status\r
-SFR(ADCCON1, 0xB4) // ADC Control 1\r
-SFR(ADCCON2, 0xB5) // ADC Control 2\r
-SFR(ADCCON3, 0xB6) // ADC Control 3\r
-SFR(IEN1, 0xB8) // Interrupt Enable 1\r
+SFR(IP0, 0xA9); // Interrupt Priority 0\r
+SFR(FWT, 0xAB); // Flash Write Timing\r
+SFR(FADDRL, 0xAC); // Flash Address Low Byte\r
+SFR(FADDRH, 0xAD); // Flash Address High Byte\r
+SFR(FCTL, 0xAE); // Flash Control\r
+SFR(FWDATA, 0xAF); // Flash Write Data\r
+SFR(ENCDI, 0xB1); // Encryption Input Data\r
+SFR(ENCDO, 0xB2); // Encryption Output Data\r
+SFR(ENCCS, 0xB3); // Encryption Control and Status\r
+SFR(ADCCON1, 0xB4); // ADC Control 1\r
+SFR(ADCCON2, 0xB5); // ADC Control 2\r
+SFR(ADCCON3, 0xB6); // ADC Control 3\r
+SFR(IEN1, 0xB8); // Interrupt Enable 1\r
SBIT(DMAIE, 0xB8, 0); // DMA Transfer Interrupt Enable\r
SBIT(T1IE, 0xB8, 1); // Timer 1 Interrupt Enable\r
SBIT(T2IE, 0xB8, 2); // Timer 2 Interrupt Enable\r
SBIT(T3IE, 0xB8, 3); // Timer 3 Interrupt Enable\r
SBIT(T4IE, 0xB8, 4); // Timer 4 Interrupt Enable\r
SBIT(P0IE, 0xB8, 5); // Port 0 Interrupt Enable\r
-SFR(IP1, 0xB9) // Interrupt Priority 1\r
-SFR(ADCL, 0xBA) // ADC Data Low\r
-SFR(ADCH, 0xBB) // ADC Data High\r
-SFR(RNDL, 0xBC) // Random Number Generator Data Low Byte\r
-SFR(RNDH, 0xBD) // Random Number Generator Data High Byte\r
-SFR(SLEEP, 0xBE) // Sleep Mode Control\r
-SFR(IRCON, 0xC0) // Interrupt Flags 4\r
+SFR(IP1, 0xB9); // Interrupt Priority 1\r
+SFR(ADCL, 0xBA); // ADC Data Low\r
+SFR(ADCH, 0xBB); // ADC Data High\r
+SFR(RNDL, 0xBC); // Random Number Generator Data Low Byte\r
+SFR(RNDH, 0xBD); // Random Number Generator Data High Byte\r
+SFR(SLEEP, 0xBE); // Sleep Mode Control\r
+SFR(IRCON, 0xC0); // Interrupt Flags 4\r
SBIT(DMAIF, 0xC0, 0); // DMA Complete Interrupt Flag\r
SBIT(T1IF, 0xC0, 1); // Timer 1 Interrupt Flag\r
SBIT(T2IF, 0xC0, 2); // Timer 2 Interrupt Flag\r
SBIT(T4IF, 0xC0, 4); // Timer 4 Interrupt Flag\r
SBIT(P0IF, 0xC0, 5); // Port 0 Interrupt Flag\r
SBIT(STIF, 0xC0, 7); // Sleep Timer Interrupt Flag\r
-SFR(U0DBUF, 0xC1) // USART 0 Receive/Transmit Data Buffer\r
-SFR(U0BAUD, 0xC2) // USART 0 Baud Rate Control\r
-SFR(T2CNF, 0xC3) // Timer 2 Configuration\r
-SFR(U0UCR, 0xC4) // USART 0 UART Control\r
-SFR(U0GCR, 0xC5) // USART 0 Generic Control\r
-SFR(CLKCON, 0xC6) // Clock Control\r
-SFR(MEMCTR, 0xC7) // Memory Arbiter Control\r
-SFR(WDCTL, 0xC9) // Watchdog Timer Control\r
-SFR(T3CNT, 0xCA) // Timer 3 Counter\r
-SFR(T3CTL, 0xCB) // Timer 3 Control\r
-SFR(T3CCTL0, 0xCC) // Timer 3 Channel 0 Capture/Compare Control\r
-SFR(T3CC0, 0xCD) // Timer 3 Channel 0 Capture/Compare Value\r
-SFR(T3CCTL1, 0xCE) // Timer 3 Channel 1 Capture/Compare Control\r
-SFR(T3CC1, 0xCF) // Timer 3 Channel 1 Capture/Compare Value\r
-SFR(PSW, 0xD0) // Program Status Word\r
+SFR(U0DBUF, 0xC1); // USART 0 Receive/Transmit Data Buffer\r
+SFR(U0BAUD, 0xC2); // USART 0 Baud Rate Control\r
+SFR(T2CNF, 0xC3); // Timer 2 Configuration\r
+SFR(U0UCR, 0xC4); // USART 0 UART Control\r
+SFR(U0GCR, 0xC5); // USART 0 Generic Control\r
+SFR(CLKCON, 0xC6); // Clock Control\r
+SFR(MEMCTR, 0xC7); // Memory Arbiter Control\r
+SFR(WDCTL, 0xC9); // Watchdog Timer Control\r
+SFR(T3CNT, 0xCA); // Timer 3 Counter\r
+SFR(T3CTL, 0xCB); // Timer 3 Control\r
+SFR(T3CCTL0, 0xCC); // Timer 3 Channel 0 Capture/Compare Control\r
+SFR(T3CC0, 0xCD); // Timer 3 Channel 0 Capture/Compare Value\r
+SFR(T3CCTL1, 0xCE); // Timer 3 Channel 1 Capture/Compare Control\r
+SFR(T3CC1, 0xCF); // Timer 3 Channel 1 Capture/Compare Value\r
+SFR(PSW, 0xD0); // Program Status Word\r
SBIT(P, 0xD0, 0); // Parity Flag\r
SBIT(F1, 0xD0, 1); // User-Defined Flag\r
SBIT(OV, 0xD0, 2); // Overflow Flag\r
SBIT(F0, 0xD0, 5); // User-Defined Flag\r
SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag\r
SBIT(CY, 0xD0, 7); // Carry Flag\r
-SFR(DMAIRQ, 0xD1) // DMA Interrupt Flag\r
-SFR(DMA1CFGL, 0xD2) // DMA Channel 1-4 Configuration Address Low Byte\r
-SFR(DMA1CFGH, 0xD3) // DMA Channel 1-4 Configuration Address High Byte\r
-SFR(DMA0CFGL, 0xD4) // DMA Channel 0 Configuration Address Low Byte\r
-SFR(DMA0CFGH, 0xD5) // DMA Channel 0 Configuration Address High Byte\r
-SFR(DMAARM, 0xD6) // DMA Channel Arm\r
-SFR(DMAREQ, 0xD7) // DMA Channel Start Request and Status\r
-SFR(TIMIF, 0xD8) // Timers 1/3/4 Interrupt Mask/Flag\r
+SFR(DMAIRQ, 0xD1); // DMA Interrupt Flag\r
+SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte\r
+SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte\r
+SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte\r
+SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte\r
+SFR(DMAARM, 0xD6); // DMA Channel Arm\r
+SFR(DMAREQ, 0xD7); // DMA Channel Start Request and Status\r
+SFR(TIMIF, 0xD8); // Timers 1/3/4 Interrupt Mask/Flag\r
SBIT(T3OVFIF, 0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending\r
SBIT(T3CH0IF, 0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending\r
SBIT(T3CH1IF, 0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending\r
SBIT(T4CH0IF, 0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending\r
SBIT(T4CH1IF, 0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending\r
SBIT(OVFIM, 0xD8, 6); // Timer 1 overflow interrupt mask\r
-SFR(RFD, 0xD9) // RF Data\r
-SFR(T1CC0L, 0xDA) // Timer 1 Channel 0 Capture/Compare Value Low\r
-SFR(T1CC0H, 0xDB) // Timer 1 Channel 0 Capture/Compare Value High\r
-SFR(T1CC1L, 0xDC) // Timer 1 Channel 1 Capture/Compare Value Low\r
-SFR(T1CC1H, 0xDD) // Timer 1 Channel 1 Capture/Compare Value High\r
-SFR(T1CC2L, 0xDE) // Timer 1 Channel 2 Capture/Compare Value Low\r
-SFR(T1CC2H, 0xDF) // Timer 1 Channel 2 Capture/Compare Value High\r
-SFR(ACC, 0xE0) // Accumulator\r
+SFR(RFD, 0xD9); // RF Data\r
+SFR(T1CC0L, 0xDA); // Timer 1 Channel 0 Capture/Compare Value Low\r
+SFR(T1CC0H, 0xDB); // Timer 1 Channel 0 Capture/Compare Value High\r
+SFR(T1CC1L, 0xDC); // Timer 1 Channel 1 Capture/Compare Value Low\r
+SFR(T1CC1H, 0xDD); // Timer 1 Channel 1 Capture/Compare Value High\r
+SFR(T1CC2L, 0xDE); // Timer 1 Channel 2 Capture/Compare Value Low\r
+SFR(T1CC2H, 0xDF); // Timer 1 Channel 2 Capture/Compare Value High\r
+SFR(ACC, 0xE0); // Accumulator\r
SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0\r
SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1\r
SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2\r
SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5\r
SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6\r
SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7\r
-SFR(RFST, 0xE1) // RF CSMA-CA / Strobe Processor\r
-SFR(T1CNTL, 0xE2) // Timer 1 Counter Low\r
-SFR(T1CNTH, 0xE3) // Timer 1 Counter High\r
-SFR(T1CTL, 0xE4) // Timer 1 Control and Status\r
-SFR(T1CCTL0, 0xE5) // Timer 1 Channel 0 Capture/Compare Control\r
-SFR(T1CCTL1, 0xE6) // Timer 1 Channel 1 Capture/Compare Control\r
-SFR(T1CCTL2, 0xE7) // Timer 1 Channel 2 Capture/Compare Control\r
-SFR(IRCON2, 0xE8) // Interrupt Flags 5\r
+SFR(RFST, 0xE1); // RF CSMA-CA / Strobe Processor\r
+SFR(T1CNTL, 0xE2); // Timer 1 Counter Low\r
+SFR(T1CNTH, 0xE3); // Timer 1 Counter High\r
+SFR(T1CTL, 0xE4); // Timer 1 Control and Status\r
+SFR(T1CCTL0, 0xE5); // Timer 1 Channel 0 Capture/Compare Control\r
+SFR(T1CCTL1, 0xE6); // Timer 1 Channel 1 Capture/Compare Control\r
+SFR(T1CCTL2, 0xE7); // Timer 1 Channel 2 Capture/Compare Control\r
+SFR(IRCON2, 0xE8); // Interrupt Flags 5\r
SBIT(P2IF, 0xE8, 0); // Port 2 Interrupt Flag\r
SBIT(UTX0IF, 0xE8, 1); // USART0 TX Interrupt Flag\r
SBIT(UTX1IF, 0xE8, 2); // USART1 TX Interrupt Flag\r
SBIT(P1IF, 0xE8, 3); // Port 1 Interrupt Flag\r
SBIT(WDTIF, 0xE8, 4); // Watchdog Timer Interrupt Flag\r
-SFR(RFIF, 0xE9) // RF Interrupt Flags\r
-SFR(T4CNT, 0xEA) // Timer 4 Counter\r
-SFR(T4CTL, 0xEB) // Timer 4 Control\r
-SFR(T4CCTL0, 0xEC) // Timer 4 Channel 0 Capture/Compare Control\r
-SFR(T4CC0, 0xED) // Timer 4 Channel 0 Capture/Compare Value\r
-SFR(T4CCTL1, 0xEE) // Timer 4 Channel 1 Capture/Compare Control\r
-SFR(T4CC1, 0xEF) // Timer 4 Channel 1 Capture/Compare Value\r
-SFR(B, 0xF0) // B Register\r
+SFR(RFIF, 0xE9); // RF Interrupt Flags\r
+SFR(T4CNT, 0xEA); // Timer 4 Counter\r
+SFR(T4CTL, 0xEB); // Timer 4 Control\r
+SFR(T4CCTL0, 0xEC); // Timer 4 Channel 0 Capture/Compare Control\r
+SFR(T4CC0, 0xED); // Timer 4 Channel 0 Capture/Compare Value\r
+SFR(T4CCTL1, 0xEE); // Timer 4 Channel 1 Capture/Compare Control\r
+SFR(T4CC1, 0xEF); // Timer 4 Channel 1 Capture/Compare Value\r
+SFR(B, 0xF0); // B Register\r
SBIT(B_0, 0xF0, 0); // Register B bit 0\r
SBIT(B_1, 0xF0, 1); // Register B bit 1\r
SBIT(B_2, 0xF0, 2); // Register B bit 2\r
SBIT(B_5, 0xF0, 5); // Register B bit 5\r
SBIT(B_6, 0xF0, 6); // Register B bit 6\r
SBIT(B_7, 0xF0, 7); // Register B bit 7\r
-SFR(PERCFG, 0xF1) // Peripheral Control\r
-SFR(ADCCFG, 0xF2) // ADC Input Configuration\r
-SFR(P0SEL, 0xF3) // Port 0 Function Select\r
-SFR(P1SEL, 0xF4) // Port 1 Function Select\r
-SFR(P2SEL, 0xF5) // Port 2 Function Select\r
-SFR(P1INP, 0xF6) // Port 1 Input Mode\r
-SFR(P2INP, 0xF7) // Port 2 Input Mode\r
-SFR(U1CSR, 0xF8) // USART 1 Control and Status\r
+SFR(PERCFG, 0xF1); // Peripheral Control\r
+SFR(ADCCFG, 0xF2); // ADC Input Configuration\r
+SFR(P0SEL, 0xF3); // Port 0 Function Select\r
+SFR(P1SEL, 0xF4); // Port 1 Function Select\r
+SFR(P2SEL, 0xF5); // Port 2 Function Select\r
+SFR(P1INP, 0xF6); // Port 1 Input Mode\r
+SFR(P2INP, 0xF7); // Port 2 Input Mode\r
+SFR(U1CSR, 0xF8); // USART 1 Control and Status\r
SBIT(ACTIVE, 0xF8, 0); // USART transmit/receive active status 0:idle 1:busy\r
SBIT(TX_BYTE, 0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted\r
SBIT(RX_BYTE, 0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready\r
SBIT(SLAVE, 0xF8, 5); // SPI master or slave mode select 0:master 1:slave\r
SBIT(RE, 0xF8, 6); // UART receiver enable 0:disabled 1:enabled\r
SBIT(MODE, 0xF8, 7); // USART mode select 0:SPI 1:UART\r
-SFR(U1DBUF, 0xF9) // USART 1 Receive/Transmit Data Buffer\r
-SFR(U1BAUD, 0xFA) // USART 1 Baud Rate Control\r
-SFR(U1UCR, 0xFB) // USART 1 UART Control\r
-SFR(U1GCR, 0xFC) // USART 1 Generic Control\r
-SFR(P0DIR, 0xFD) // Port 0 Direction\r
-SFR(P1DIR, 0xFE) // Port 1 Direction\r
-SFR(P2DIR, 0xFF) // Port 2 Direction\r
+SFR(U1DBUF, 0xF9); // USART 1 Receive/Transmit Data Buffer\r
+SFR(U1BAUD, 0xFA); // USART 1 Baud Rate Control\r
+SFR(U1UCR, 0xFB); // USART 1 UART Control\r
+SFR(U1GCR, 0xFC); // USART 1 Generic Control\r
+SFR(P0DIR, 0xFD); // Port 0 Direction\r
+SFR(P1DIR, 0xFE); // Port 1 Direction\r
+SFR(P2DIR, 0xFF); // Port 2 Direction\r
\r
// From Table 45 : Overview of RF registers\r
\r
\r
// SFRs also accesible through XDATA space\r
\r
-SFRX(X_U0CSR, 0xDF86) // USART 0 Control and Status\r
-SFRX(X_P0IFG, 0xDF89) // Port 0 Interrupt Status Flag\r
-SFRX(X_P1IFG, 0xDF8A) // Port 1 Interrupt Status Flag\r
-SFRX(X_P2IFG, 0xDF8B) // Port 2 Interrupt Status Flag\r
-SFRX(X_PICTL, 0xDF8C) // Port Interrupt Control\r
-SFRX(X_P1IEN, 0xDF8D) // Port 1 Interrupt Mask\r
-SFRX(X_P0INP, 0xDF8F) // Port 0 Input Mode\r
-SFRX(X_RFIM, 0xDF91) // RF Interrupt Mask\r
-SFRX(X_MPAGE, 0xDF93) // Memory Page Select\r
-SFRX(X_T2CMP, 0xDF94) // Timer 2 Compare Value\r
-SFRX(X_ST0, 0xDF95) // Sleep Timer 0\r
-SFRX(X_ST1, 0xDF96) // Sleep Timer 1\r
-SFRX(X_ST2, 0xDF97) // Sleep Timer 2\r
-SFRX(X_T2PEROF0, 0xDF9C) // Timer 2 Overflow Capture/Compare 0\r
-SFRX(X_T2PEROF1, 0xDF9D) // Timer 2 Overflow Capture/Compare 1\r
-SFRX(X_T2PEROF2, 0xDF9E) // Timer 2 Overflow Capture/Compare 2\r
-SFRX(X_T2OF0, 0xDFA1) // Timer 2 Overflow Count 0\r
-SFRX(X_T2OF1, 0xDFA2) // Timer 2 Overflow Count 1\r
-SFRX(X_T2OF2, 0xDFA3) // Timer 2 Overflow Count 2\r
-SFRX(X_T2CAPLPL, 0xDFA4) // Timer 2 Period Low Byte\r
-SFRX(X_T2CAPHPH, 0xDFA5) // Timer 2 Period High Byte\r
-SFRX(X_T2TLD, 0xDFA6) // Timer 2 Timer Value Low Byte\r
-SFRX(X_T2THD, 0xDFA7) // Timer 2 Timer Value High Byte\r
-SFRX(X_FWT, 0xDFAB) // Flash Write Timing\r
-SFRX(X_FADDRL, 0xDFAC) // Flash Address Low Byte\r
-SFRX(X_FADDRH, 0xDFAD) // Flash Address High Byte\r
-SFRX(X_FCTL, 0xDFAE) // Flash Control\r
-SFRX(X_FWDATA, 0xDFAF) // Flash Write Data\r
-SFRX(X_ENCDI, 0xDFB1) // Encryption Input Data\r
-SFRX(X_ENCDO, 0xDFB2) // Encryption Output Data\r
-SFRX(X_ENCCS, 0xDFB3) // Encryption Control and Status\r
-SFRX(X_ADCCON1, 0xDFB4) // ADC Control 1\r
-SFRX(X_ADCCON2, 0xDFB5) // ADC Control 2\r
-SFRX(X_ADCCON3, 0xDFB6) // ADC Control 3\r
-SFRX(X_ADCL, 0xDFBA) // ADC Data Low\r
-SFRX(X_ADCH, 0xDFBB) // ADC Data High\r
-SFRX(X_RNDL, 0xDFBC) // Random Number Generator Data Low Byte\r
-SFRX(X_RNDH, 0xDFBD) // Random Number Generator Data High Byte\r
-SFRX(X_SLEEP, 0xDFBE) // Sleep Mode Control\r
-SFRX(X_U0DBUF, 0xDFC1) // USART 0 Receive/Transmit Data Buffer\r
-SFRX(X_U0BAUD, 0xDFC2) // USART 0 Baud Rate Control\r
-SFRX(X_T2CNF, 0xDFC3) // Timer 2 Configuration\r
-SFRX(X_U0UCR, 0xDFC4) // USART 0 UART Control\r
-SFRX(X_U0GCR, 0xDFC5) // USART 0 Generic Control\r
-SFRX(X_CLKCON, 0xDFC6) // Clock Control\r
-SFRX(X_MEMCTR, 0xDFC7) // Memory Arbiter Control\r
-SFRX(X_WDCTL, 0xDFC9) // Watchdog Timer Control\r
-SFRX(X_T3CNT, 0xDFCA) // Timer 3 Counter\r
-SFRX(X_T3CTL, 0xDFCB) // Timer 3 Control\r
-SFRX(X_T3CCTL0, 0xDFCC) // Timer 3 Channel 0 Capture/Compare Control\r
-SFRX(X_T3CC0, 0xDFCD) // Timer 3 Channel 0 Capture/Compare Value\r
-SFRX(X_T3CCTL1, 0xDFCE) // Timer 3 Channel 1 Capture/Compare Control\r
-SFRX(X_T3CC1, 0xDFCF) // Timer 3 Channel 1 Capture/Compare Value\r
-SFRX(X_DMAIRQ, 0xDFD1) // DMA Interrupt Flag\r
-SFRX(X_DMA1CFGL, 0xDFD2) // DMA Channel 1-4 Configuration Address Low Byte\r
-SFRX(X_DMA1CFGH, 0xDFD3) // DMA Channel 1-4 Configuration Address High Byte\r
-SFRX(X_DMA0CFGL, 0xDFD4) // DMA Channel 0 Configuration Address Low Byte\r
-SFRX(X_DMA0CFGH, 0xDFD5) // DMA Channel 0 Configuration Address High Byte\r
-SFRX(X_DMAARM, 0xDFD6) // DMA Channel Arm\r
-SFRX(X_DMAREQ, 0xDFD7) // DMA Channel Start Request and Status\r
-SFRX(X_TIMIF, 0xDFD8) // Timers 1/3/4 Interrupt Mask/Flag\r
-SFRX(X_RFD, 0xDFD9) // RF Data\r
-SFRX(X_T1CC0L, 0xDFDA) // Timer 1 Channel 0 Capture/Compare Value Low\r
-SFRX(X_T1CC0H, 0xDFDB) // Timer 1 Channel 0 Capture/Compare Value High\r
-SFRX(X_T1CC1L, 0xDFDC) // Timer 1 Channel 1 Capture/Compare Value Low\r
-SFRX(X_T1CC1H, 0xDFDD) // Timer 1 Channel 1 Capture/Compare Value High\r
-SFRX(X_T1CC2L, 0xDFDE) // Timer 1 Channel 2 Capture/Compare Value Low\r
-SFRX(X_T1CC2H, 0xDFDF) // Timer 1 Channel 2 Capture/Compare Value High\r
-SFRX(X_RFST, 0xDFE1) // RF CSMA-CA / Strobe Processor\r
-SFRX(X_T1CNTL, 0xDFE2) // Timer 1 Counter Low\r
-SFRX(X_T1CNTH, 0xDFE3) // Timer 1 Counter High\r
-SFRX(X_T1CTL, 0xDFE4) // Timer 1 Control and Status\r
-SFRX(X_T1CCTL0, 0xDFE5) // Timer 1 Channel 0 Capture/Compare Control\r
-SFRX(X_T1CCTL1, 0xDFE6) // Timer 1 Channel 1 Capture/Compare Control\r
-SFRX(X_T1CCTL2, 0xDFE7) // Timer 1 Channel 2 Capture/Compare Control\r
-SFRX(X_RFIF, 0xDFE9) // RF Interrupt Flags\r
-SFRX(X_T4CNT, 0xDFEA) // Timer 4 Counter\r
-SFRX(X_T4CTL, 0xDFEB) // Timer 4 Control\r
-SFRX(X_T4CCTL0, 0xDFEC) // Timer 4 Channel 0 Capture/Compare Control\r
-SFRX(X_T4CC0, 0xDFED) // Timer 4 Channel 0 Capture/Compare Value\r
-SFRX(X_T4CCTL1, 0xDFEE) // Timer 4 Channel 1 Capture/Compare Control\r
-SFRX(X_T4CC1, 0xDFEF) // Timer 4 Channel 1 Capture/Compare Value\r
-SFRX(X_PERCFG, 0xDFF1) // Peripheral Control\r
-SFRX(X_ADCCFG, 0xDFF2) // ADC Input Configuration\r
-SFRX(X_P0SEL, 0xDFF3) // Port 0 Function Select\r
-SFRX(X_P1SEL, 0xDFF4) // Port 1 Function Select\r
-SFRX(X_P2SEL, 0xDFF5) // Port 2 Function Select\r
-SFRX(X_P1INP, 0xDFF6) // Port 1 Input Mode\r
-SFRX(X_P2INP, 0xDFF7) // Port 2 Input Mode\r
-SFRX(X_U1CSR, 0xDFF8) // USART 1 Control and Status\r
-SFRX(X_U1DBUF, 0xDFF9) // USART 1 Receive/Transmit Data Buffer\r
-SFRX(X_U1BAUD, 0xDFFA) // USART 1 Baud Rate Control\r
-SFRX(X_U1UCR, 0xDFFB) // USART 1 UART Control\r
-SFRX(X_U1GCR, 0xDFFC) // USART 1 Generic Control\r
-SFRX(X_P0DIR, 0xDFFD) // Port 0 Direction\r
-SFRX(X_P1DIR, 0xDFFE) // Port 1 Direction\r
-SFRX(X_P2DIR, 0xDFFF) // Port 2 Direction\r
+SFRX(X_U0CSR, 0xDF86); // USART 0 Control and Status\r
+SFRX(X_P0IFG, 0xDF89); // Port 0 Interrupt Status Flag\r
+SFRX(X_P1IFG, 0xDF8A); // Port 1 Interrupt Status Flag\r
+SFRX(X_P2IFG, 0xDF8B); // Port 2 Interrupt Status Flag\r
+SFRX(X_PICTL, 0xDF8C); // Port Interrupt Control\r
+SFRX(X_P1IEN, 0xDF8D); // Port 1 Interrupt Mask\r
+SFRX(X_P0INP, 0xDF8F); // Port 0 Input Mode\r
+SFRX(X_RFIM, 0xDF91); // RF Interrupt Mask\r
+SFRX(X_MPAGE, 0xDF93); // Memory Page Select\r
+SFRX(X_T2CMP, 0xDF94); // Timer 2 Compare Value\r
+SFRX(X_ST0, 0xDF95); // Sleep Timer 0\r
+SFRX(X_ST1, 0xDF96); // Sleep Timer 1\r
+SFRX(X_ST2, 0xDF97); // Sleep Timer 2\r
+SFRX(X_T2PEROF0, 0xDF9C); // Timer 2 Overflow Capture/Compare 0\r
+SFRX(X_T2PEROF1, 0xDF9D); // Timer 2 Overflow Capture/Compare 1\r
+SFRX(X_T2PEROF2, 0xDF9E); // Timer 2 Overflow Capture/Compare 2\r
+SFRX(X_T2OF0, 0xDFA1); // Timer 2 Overflow Count 0\r
+SFRX(X_T2OF1, 0xDFA2); // Timer 2 Overflow Count 1\r
+SFRX(X_T2OF2, 0xDFA3); // Timer 2 Overflow Count 2\r
+SFRX(X_T2CAPLPL, 0xDFA4); // Timer 2 Period Low Byte\r
+SFRX(X_T2CAPHPH, 0xDFA5); // Timer 2 Period High Byte\r
+SFRX(X_T2TLD, 0xDFA6); // Timer 2 Timer Value Low Byte\r
+SFRX(X_T2THD, 0xDFA7); // Timer 2 Timer Value High Byte\r
+SFRX(X_FWT, 0xDFAB); // Flash Write Timing\r
+SFRX(X_FADDRL, 0xDFAC); // Flash Address Low Byte\r
+SFRX(X_FADDRH, 0xDFAD); // Flash Address High Byte\r
+SFRX(X_FCTL, 0xDFAE); // Flash Control\r
+SFRX(X_FWDATA, 0xDFAF); // Flash Write Data\r
+SFRX(X_ENCDI, 0xDFB1); // Encryption Input Data\r
+SFRX(X_ENCDO, 0xDFB2); // Encryption Output Data\r
+SFRX(X_ENCCS, 0xDFB3); // Encryption Control and Status\r
+SFRX(X_ADCCON1, 0xDFB4); // ADC Control 1\r
+SFRX(X_ADCCON2, 0xDFB5); // ADC Control 2\r
+SFRX(X_ADCCON3, 0xDFB6); // ADC Control 3\r
+SFRX(X_ADCL, 0xDFBA); // ADC Data Low\r
+SFRX(X_ADCH, 0xDFBB); // ADC Data High\r
+SFRX(X_RNDL, 0xDFBC); // Random Number Generator Data Low Byte\r
+SFRX(X_RNDH, 0xDFBD); // Random Number Generator Data High Byte\r
+SFRX(X_SLEEP, 0xDFBE); // Sleep Mode Control\r
+SFRX(X_U0DBUF, 0xDFC1); // USART 0 Receive/Transmit Data Buffer\r
+SFRX(X_U0BAUD, 0xDFC2); // USART 0 Baud Rate Control\r
+SFRX(X_T2CNF, 0xDFC3); // Timer 2 Configuration\r
+SFRX(X_U0UCR, 0xDFC4); // USART 0 UART Control\r
+SFRX(X_U0GCR, 0xDFC5); // USART 0 Generic Control\r
+SFRX(X_CLKCON, 0xDFC6); // Clock Control\r
+SFRX(X_MEMCTR, 0xDFC7); // Memory Arbiter Control\r
+SFRX(X_WDCTL, 0xDFC9); // Watchdog Timer Control\r
+SFRX(X_T3CNT, 0xDFCA); // Timer 3 Counter\r
+SFRX(X_T3CTL, 0xDFCB); // Timer 3 Control\r
+SFRX(X_T3CCTL0, 0xDFCC); // Timer 3 Channel 0 Capture/Compare Control\r
+SFRX(X_T3CC0, 0xDFCD); // Timer 3 Channel 0 Capture/Compare Value\r
+SFRX(X_T3CCTL1, 0xDFCE); // Timer 3 Channel 1 Capture/Compare Control\r
+SFRX(X_T3CC1, 0xDFCF); // Timer 3 Channel 1 Capture/Compare Value\r
+SFRX(X_DMAIRQ, 0xDFD1); // DMA Interrupt Flag\r
+SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte\r
+SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte\r
+SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte\r
+SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte\r
+SFRX(X_DMAARM, 0xDFD6); // DMA Channel Arm\r
+SFRX(X_DMAREQ, 0xDFD7); // DMA Channel Start Request and Status\r
+SFRX(X_TIMIF, 0xDFD8); // Timers 1/3/4 Interrupt Mask/Flag\r
+SFRX(X_RFD, 0xDFD9); // RF Data\r
+SFRX(X_T1CC0L, 0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low\r
+SFRX(X_T1CC0H, 0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High\r
+SFRX(X_T1CC1L, 0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low\r
+SFRX(X_T1CC1H, 0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High\r
+SFRX(X_T1CC2L, 0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low\r
+SFRX(X_T1CC2H, 0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High\r
+SFRX(X_RFST, 0xDFE1); // RF CSMA-CA / Strobe Processor\r
+SFRX(X_T1CNTL, 0xDFE2); // Timer 1 Counter Low\r
+SFRX(X_T1CNTH, 0xDFE3); // Timer 1 Counter High\r
+SFRX(X_T1CTL, 0xDFE4); // Timer 1 Control and Status\r
+SFRX(X_T1CCTL0, 0xDFE5); // Timer 1 Channel 0 Capture/Compare Control\r
+SFRX(X_T1CCTL1, 0xDFE6); // Timer 1 Channel 1 Capture/Compare Control\r
+SFRX(X_T1CCTL2, 0xDFE7); // Timer 1 Channel 2 Capture/Compare Control\r
+SFRX(X_RFIF, 0xDFE9); // RF Interrupt Flags\r
+SFRX(X_T4CNT, 0xDFEA); // Timer 4 Counter\r
+SFRX(X_T4CTL, 0xDFEB); // Timer 4 Control\r
+SFRX(X_T4CCTL0, 0xDFEC); // Timer 4 Channel 0 Capture/Compare Control\r
+SFRX(X_T4CC0, 0xDFED); // Timer 4 Channel 0 Capture/Compare Value\r
+SFRX(X_T4CCTL1, 0xDFEE); // Timer 4 Channel 1 Capture/Compare Control\r
+SFRX(X_T4CC1, 0xDFEF); // Timer 4 Channel 1 Capture/Compare Value\r
+SFRX(X_PERCFG, 0xDFF1); // Peripheral Control\r
+SFRX(X_ADCCFG, 0xDFF2); // ADC Input Configuration\r
+SFRX(X_P0SEL, 0xDFF3); // Port 0 Function Select\r
+SFRX(X_P1SEL, 0xDFF4); // Port 1 Function Select\r
+SFRX(X_P2SEL, 0xDFF5); // Port 2 Function Select\r
+SFRX(X_P1INP, 0xDFF6); // Port 1 Input Mode\r
+SFRX(X_P2INP, 0xDFF7); // Port 2 Input Mode\r
+SFRX(X_U1CSR, 0xDFF8); // USART 1 Control and Status\r
+SFRX(X_U1DBUF, 0xDFF9); // USART 1 Receive/Transmit Data Buffer\r
+SFRX(X_U1BAUD, 0xDFFA); // USART 1 Baud Rate Control\r
+SFRX(X_U1UCR, 0xDFFB); // USART 1 UART Control\r
+SFRX(X_U1GCR, 0xDFFC); // USART 1 Generic Control\r
+SFRX(X_P0DIR, 0xDFFD); // Port 0 Direction\r
+SFRX(X_P1DIR, 0xDFFE); // Port 1 Direction\r
+SFRX(X_P2DIR, 0xDFFF); // Port 2 Direction\r
\r
#endif //REG_CC2430_H\r
projects / fw / sdcc / blobdiff