* debugger/mcs51/break.c: bugfix from patch 1989966, thanks Risto Huotari

[fw/sdcc] / device / include / mcs51 / at89c51ed2.h

diff --git a/device/include/mcs51/at89c51ed2.h b/device/include/mcs51/at89c51ed2.h
index fc04c6bbb0f0556670c77b86bac7173f6e43e41d..c1f9a0b050f3f66a1b76d65bee612051a49b540b 100644 (file)
--- a/device/include/mcs51/at89c51ed2.h
+++ b/device/include/mcs51/at89c51ed2.h
@@ -54,7 +54,7 @@ __sfr __at (0xA2) AUXR1;      //Auxiliary function register 1
        #define DPS 0x01                //Data pointer select.
 
 __sfr __at (0x97) CKRL;     //Clock Reload Register
-__sfr __at (0x8F) CKCKON0;  //Clock control Register 0
+__sfr __at (0x8F) CKCON0;   //Clock control Register 0
     #define WDTX2 0x40      //Watch Dog Clock speed '1'=12 ck/cy, '0'=6 ck/cy
     #define PCAX2 0x20      //Programmable Counter Array Clock speed '1'=12 ck/cy, '0'=6 ck/cy
     #define SIX2  0x10      //Enhanced UART Clock (Mode 0 and 2) speed '1'=12 ck/cy, '0'=6 ck/cy
@@ -62,7 +62,7 @@ __sfr __at (0x8F) CKCKON0;  //Clock control Register 0
     #define T1X2  0x04      //Timer1 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
     #define T0X2  0x02      //Timer0 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
     #define X2    0x01      //CPU Clock '0'=12 ck/cy, '1'=6 ck/cy
-__sfr __at (0x8F) CKCKON1;  //Clock control Register 1
+__sfr __at (0xAF) CKCON1;   //Clock control Register 1
     #define XPIX2 0x01      //SPI Clock speed '1'=12 ck/cy, '0'=6 ck/cy
 
 __sfr __at (0xFA) CCAP0H;      //Module 0 Capture HIGH. 
@@ -131,7 +131,7 @@ __sfr __at (0xB8) IPL0;         //Interrupt Priority 0 LOW
        __sbit __at (0xB9) PT0L;//Timer 0 Interrupt Priority Low Bit.
        __sbit __at (0xB8) PX0L;//External Interrupt 0 Priority Low Bit.
 
-__sfr __at (0xB7) IP0H;                //Interrupt Priority 0 HIGH  
+__sfr __at (0xB7) IPH0;                //Interrupt Priority 0 HIGH  
        #define PPCH 0x40               //PCA Interrupt Priority High Bit.
        #define PT2H 0x20               //Timer 2 Interrupt Priority High Bit.
        #define PHS  0x10               //Serial Port Interrupt Priority High Bit.