--- /dev/null
+/*--------------------------------------------------------------------------\r
+P89LPC932.H\r
+(English)\r
+This header allows to use the microcontroler Philips P89LPC932\r
+with the compiler SDCC.\r
+\r
+Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com.\r
+\r
+ This library is free software; you can redistribute it and/or\r
+ modify it under the terms of the GNU Lesser General Public\r
+ License as published by the Free Software Foundation; either\r
+ version 2.1 of the License, or (at your option) any later version.\r
+\r
+ This library is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+ Lesser General Public License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public\r
+ License along with this library; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+(Spanish-Español)\r
+Archivo encabezador para el ucontrolador Philips P89LPC932.\r
+Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com\r
+Uso libre\r
+--------------------------------------------------------------------------*/\r
+#ifndef __REG932_H__\r
+#define __REG932_H__\r
+\r
+/* BYTE Registers */\r
+__sfr __at (0x80) P0 ;\r
+__sfr __at (0x90) P1 ;\r
+__sfr __at (0xA0) P2 ;\r
+__sfr __at (0xB0) P3 ;\r
+__sfr __at (0xD0) PSW ;\r
+__sfr __at (0xE0) ACC ;\r
+__sfr __at (0xF0) B ;\r
+__sfr __at (0x81) SP ;\r
+__sfr __at (0x82) DPL ;\r
+__sfr __at (0x83) DPH ;\r
+__sfr __at (0x87) PCON ;\r
+__sfr __at (0x88) TCON ;\r
+__sfr __at (0x89) TMOD ;\r
+__sfr __at (0x8A) TL0 ;\r
+__sfr __at (0x8B) TL1 ;\r
+__sfr __at (0x8C) TH0 ;\r
+__sfr __at (0x8D) TH1 ;\r
+__sfr __at (0xA8) IEN0 ;\r
+__sfr __at (0xB8) IP0 ;\r
+__sfr __at (0x98) SCON ;\r
+__sfr __at (0x99) SBUF ;\r
+\r
+\r
+__sfr __at (0xA2) AUXR1 ;\r
+__sfr __at (0xA9) SADDR ;\r
+__sfr __at (0xB9) SADEN ;\r
+__sfr __at (0xCC) TL2 ;\r
+__sfr __at (0xCD) TH2 ;\r
+__sfr __at (0xBE) BRGR0 ;\r
+__sfr __at (0xBF) BRGR1 ;\r
+__sfr __at (0xBD) BRGCON ;\r
+__sfr __at (0xEA) CCCRA ;\r
+__sfr __at (0xEB) CCCRB ;\r
+__sfr __at (0xEC) CCCRC ;\r
+__sfr __at (0xED) CCCRD ;\r
+__sfr __at (0xAC) CMP1 ;\r
+__sfr __at (0xAD) CMP2 ;\r
+__sfr __at (0xF1) DEECON ;\r
+__sfr __at (0xF2) DEEDAT ;\r
+__sfr __at (0xF3) DEEADR ;\r
+__sfr __at (0x95) DIVM ;\r
+__sfr __at (0xDB) I2ADR ;\r
+__sfr __at (0xD8) I2CON ;\r
+__sfr __at (0xDA) I2DAT ;\r
+__sfr __at (0xDD) I2SCLH ;\r
+__sfr __at (0xDC) I2SCLL ;\r
+__sfr __at (0xD9) I2STAT ;\r
+__sfr __at (0xAB) ICRAH ;\r
+__sfr __at (0xAA) ICRAL ;\r
+__sfr __at (0xAF) ICRBH ;\r
+__sfr __at (0xAE) ICRBL ;\r
+__sfr __at (0xE8) IEN1 ;\r
+__sfr __at (0xF8) IP1 ;\r
+__sfr __at (0xF7) IP1H ;\r
+__sfr __at (0x94) KBCON ;\r
+__sfr __at (0x86) KBMASK ;\r
+__sfr __at (0x93) KBPATN ;\r
+__sfr __at (0xEF) OCRAH ;\r
+__sfr __at (0xEE) OCRAL ;\r
+__sfr __at (0xFB) OCRBH ;\r
+__sfr __at (0xFA) OCRBL ;\r
+__sfr __at (0xFD) OCRCH ;\r
+__sfr __at (0xFC) OCRCL ;\r
+__sfr __at (0xFF) OCRDH ;\r
+__sfr __at (0xFE) OCRDL ;\r
+__sfr __at (0x84) P0M1 ;\r
+__sfr __at (0x85) P0M2 ;\r
+__sfr __at (0x91) P1M1 ;\r
+__sfr __at (0x92) P1M2 ;\r
+__sfr __at (0xA4) P2M1 ;\r
+__sfr __at (0xA5) P2M2 ;\r
+__sfr __at (0xB1) P3M1 ;\r
+__sfr __at (0xB2) P3M2 ;\r
+__sfr __at (0xB5) PCONA ;\r
+__sfr __at (0xF6) PT0AD ;\r
+__sfr __at (0xDF) RSTSRC ;\r
+__sfr __at (0xD1) RTCCON ;\r
+__sfr __at (0xD2) RTCH ;\r
+__sfr __at (0xD3) RTCL ;\r
+__sfr __at (0xBA) SSTAT ;\r
+__sfr __at (0xE2) SPCTL ;\r
+__sfr __at (0xE1) SPSTAT ;\r
+__sfr __at (0xE3) SPDAT ;\r
+__sfr __at (0x8F) TAMOD ;\r
+__sfr __at (0xC8) TCR20 ;\r
+__sfr __at (0xF9) TCR21 ;\r
+__sfr __at (0xC9) TICR2 ;\r
+__sfr __at (0xE9) TIFR2 ;\r
+__sfr __at (0xDE) TISE2 ;\r
+__sfr __at (0xCF) TOR2H ;\r
+__sfr __at (0xCE) TOR2L ;\r
+__sfr __at (0xCB) TPCR2H ;\r
+__sfr __at (0xCA) TPCR2L ;\r
+__sfr __at (0x96) TRIM ;\r
+__sfr __at (0xA7) WDCON ;\r
+__sfr __at (0xC1) WDL ;\r
+__sfr __at (0xC2) WFEED1 ;\r
+__sfr __at (0xC3) WFEED2 ;\r
+__sfr __at (0xB7) IP0H ;\r
+\r
+/* BIT Registers */\r
+/* PSW */\r
+__sbit __at (0xD7) PSW_7;\r
+__sbit __at (0xD6) PSW_6;\r
+__sbit __at (0xD5) PSW_5;\r
+__sbit __at (0xD4) PSW_4;\r
+__sbit __at (0xD3) PSW_3;\r
+__sbit __at (0xD2) PSW_2;\r
+__sbit __at (0xD1) PSW_1;\r
+__sbit __at (0xD0) PSW_0;\r
+\r
+#define CY PSW_7\r
+#define AC PSW_6\r
+#define F0 PSW_5\r
+#define RS1 PSW_4\r
+#define RS0 PSW_3\r
+#define OV PSW_2\r
+#define F1 PSW_1\r
+#define P PSW_0\r
+\r
+/* TCON */\r
+__sbit __at (0x8F) TCON_7;\r
+__sbit __at (0x8E) TCON_6;\r
+__sbit __at (0x8D) TCON_5;\r
+__sbit __at (0x8C) TCON_4;\r
+__sbit __at (0x8B) TCON_3;\r
+__sbit __at (0x8A) TCON_2;\r
+__sbit __at (0x89) TCON_1;\r
+__sbit __at (0x88) TCON_0;\r
+\r
+#define TF1 TCON_7\r
+#define TR1 TCON_6\r
+#define TF0 TCON_5\r
+#define TR0 TCON_4\r
+#define IE1 TCON_3\r
+#define IT1 TCON_2\r
+#define IE0 TCON_1\r
+#define IT0 TCON_0\r
+\r
+/* IEN0 */\r
+__sbit __at (0xAF) IEN0_7;\r
+__sbit __at (0xAE) IEN0_6;\r
+__sbit __at (0xAD) IEN0_5;\r
+__sbit __at (0xAC) IEN0_4; // alternatively "ESR"\r
+__sbit __at (0xAC) IEN0_4;\r
+__sbit __at (0xAB) IEN0_3;\r
+__sbit __at (0xAA) IEN0_2;\r
+__sbit __at (0xA9) IEN0_1;\r
+__sbit __at (0xA8) IEN0_0;\r
+\r
+#define EA IEN0_7\r
+#define EWDRT IEN0_6\r
+#define EBO IEN0_5\r
+#define ES IEN0_4 // alternatively "ESR"\r
+#define ESR IEN0_4\r
+#define ET1 IEN0_3\r
+#define EX1 IEN0_2\r
+#define ET0 IEN0_1\r
+#define EX0 IEN0_0\r
+\r
+/* IEN1 */\r
+__sbit __at (0xEF) IEN1_7;\r
+__sbit __at (0xEE) IEN1_6;\r
+__sbit __at (0xEC) IEN1_4;\r
+__sbit __at (0xEB) IEN1_3;\r
+__sbit __at (0xEA) IEN1_2;\r
+__sbit __at (0xE9) IEN1_1;\r
+__sbit __at (0xE8) IEN1_0;\r
+\r
+#define EIEE IEN1_7\r
+#define EST IEN1_6\r
+#define ECCU IEN1_4\r
+#define ESPI IEN1_3\r
+#define EC IEN1_2\r
+#define EKBI IEN1_1\r
+#define EI2C IEN1_0\r
+\r
+/* IP0 */\r
+__sbit __at (0xBE) IP0_6;\r
+__sbit __at (0xBD) IP0_5;\r
+__sbit __at (0xBC) IP0_4; // alternatively "PSR"\r
+__sbit __at (0xBC) IP0_4;\r
+__sbit __at (0xBB) IP0_3;\r
+__sbit __at (0xBA) IP0_2;\r
+__sbit __at (0xB9) IP0_1;\r
+__sbit __at (0xB8) IP0_0;\r
+\r
+#define PWDRT IP0_6\r
+#define PB0 IP0_5\r
+#define PS IP0_4 // alternatively "PSR"\r
+#define PSR IP0_4\r
+#define PT1 IP0_3\r
+#define PX1 IP0_2\r
+#define PT0 IP0_1\r
+#define PX0 IP0_0\r
+\r
+/* SCON */\r
+__sbit __at (0x9F) SCON_7; // alternatively "FE"\r
+__sbit __at (0x9E) SCON_6;\r
+__sbit __at (0x9D) SCON_5;\r
+__sbit __at (0x9C) SCON_4;\r
+__sbit __at (0x9B) SCON_3;\r
+__sbit __at (0x9A) SCON_2;\r
+__sbit __at (0x99) SCON_1;\r
+__sbit __at (0x98) SCON_0;\r
+\r
+#define SM0 SCON_7 // alternatively "FE"\r
+#define FE SCON_7\r
+#define SM1 SCON_6\r
+#define SM2 SCON_5\r
+#define REN SCON_4\r
+#define TB8 SCON_3\r
+#define RB8 SCON_2\r
+#define TI SCON_1\r
+#define RI SCON_0\r
+\r
+/* I2CON */\r
+__sbit __at (0xDE) I2CON_6;\r
+__sbit __at (0xDD) I2CON_5;\r
+__sbit __at (0xDC) I2CON_4;\r
+__sbit __at (0xDB) I2CON_3;\r
+__sbit __at (0xDA) I2CON_2;\r
+__sbit __at (0xD8) I2CON_0;\r
+\r
+#define I2EN I2CON_6;\r
+#define STA I2CON_5;\r
+#define STO I2CON_4;\r
+#define SI I2CON_3;\r
+#define AA I2CON_2;\r
+#define CRSEL I2CON_0;\r
+\r
+/* P0 */\r
+__sbit __at (0x87) P0_7;\r
+__sbit __at (0x86) P0_6; // alternatively "CMP1"\r
+__sbit __at (0x85) P0_5;\r
+__sbit __at (0x84) P0_4;\r
+__sbit __at (0x83) P0_3;\r
+__sbit __at (0x82) P0_2;\r
+__sbit __at (0x81) P0_1;\r
+__sbit __at (0x80) P0_0; // alternatively "CMP2"\r
+\r
+#define KB7 P0_7 // alternatively "T1"\r
+#define T1 P0_7\r
+#define KB6 P0_6 // alternatively "CMP1"\r
+#define CMP1 P0_6\r
+#define KB5 P0_5\r
+#define KB4 P0_4\r
+#define KB3 P0_3\r
+#define KB2 P0_2\r
+#define KB1 P0_1\r
+#define KB0 P0_0 // alternatively "CMP2"\r
+#define CMP2 P0_0\r
+\r
+/* P1 */\r
+__sbit __at (0x97) P1_7;\r
+__sbit __at (0x96) P1_6;\r
+__sbit __at (0x95) P1_5;\r
+__sbit __at (0x94) P1_4;\r
+__sbit __at (0x93) P1_3;\r
+__sbit __at (0x92) P1_2;\r
+__sbit __at (0x91) P1_1;\r
+__sbit __at (0x90) P1_0;\r
+\r
+#define OCC P1_7\r
+#define OCB P1_6\r
+#define RST P1_5\r
+#define INT1 P1_4\r
+#define INT0 P1_3 // alternatively "SDA"\r
+#define SDA P1_3\r
+#define T0 P1_2 // alternatively "SCL"\r
+#define SCL P1_2\r
+#define RxD P1_1\r
+#define TxD P1_0\r
+\r
+/* P2 */\r
+__sbit __at (0xA7) P2_7;\r
+__sbit __at (0xA6) P2_6;\r
+__sbit __at (0xA5) P2_5;\r
+__sbit __at (0xA4) P2_4;\r
+__sbit __at (0xA3) P2_3;\r
+__sbit __at (0xA2) P2_2;\r
+__sbit __at (0xA1) P2_1;\r
+__sbit __at (0xA0) P2_0;\r
+\r
+#define ICA P2_7\r
+#define OCA P2_6\r
+#define SPICLK P2_5\r
+#define SS P2_4\r
+#define MISO P2_3\r
+#define MOSI P2_2\r
+#define OCD P2_1\r
+#define ICB P2_0\r
+\r
+/* P3 */\r
+__sbit __at (0xB1) P3_1;\r
+__sbit __at (0xB0) P3_0;\r
+\r
+#define XTAL1 P3_1\r
+#define XTAL2 P3_0\r
+\r
+/* TCR20 */\r
+__sbit __at (0xCF) TCR20_7;\r
+__sbit __at (0xCE) TCR20_6;\r
+__sbit __at (0xCD) TCR20_5;\r
+__sbit __at (0xCC) TCR20_4;\r
+__sbit __at (0xCB) TCR20_3;\r
+__sbit __at (0xCA) TCR20_2;\r
+__sbit __at (0xC9) TCR20_1;\r
+__sbit __at (0xC8) TCR20_0;\r
+\r
+#define PLLEN TCR20_7\r
+#define HLTRN TCR20_6\r
+#define HLTEN TCR20_5\r
+#define ALTCD TCR20_4\r
+#define ALTAB TCR20_3\r
+#define TDIR2 TCR20_2\r
+#define TMOD21 TCR20_1\r
+#define TMOD20 TCR20_0\r
+\r
+#endif\r
projects / fw / sdcc / blobdiff