--- /dev/null
+/*--------------------------------------------------------------------------\r
+P89LPC901.H\r
+(English)\r
+This header allows to use the microcontroler Philips P89LPC901\r
+with the compiler SDCC.\r
+\r
+Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com.\r
+\r
+ This library is free software; you can redistribute it and/or\r
+ modify it under the terms of the GNU Lesser General Public\r
+ License as published by the Free Software Foundation; either\r
+ version 2.1 of the License, or (at your option) any later version.\r
+\r
+ This library is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+ Lesser General Public License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public\r
+ License along with this library; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+(Spanish-Español)\r
+Archivo encabezador para el ucontrolador Philips P89LPC901.\r
+Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com\r
+Uso libre\r
+--------------------------------------------------------------------------*/\r
+\r
+#ifndef __REG901_H__\r
+#define __REG901_H__\r
+\r
+/* BYTE Registers */\r
+__sfr __at (0x80) P0 ;\r
+__sfr __at (0x84) P0M1 ;\r
+__sfr __at (0x85) P0M2 ;\r
+\r
+__sfr __at (0x90) P1 ;\r
+__sfr __at (0x91) P1M1 ;\r
+__sfr __at (0x92) P1M2 ;\r
+\r
+__sfr __at (0xB0) P3 ;\r
+__sfr __at (0xB1) P3M1 ;\r
+__sfr __at (0xB2) P3M2 ;\r
+//------------------\r
+__sfr __at (0xD0) PSW ;\r
+__sfr __at (0xE0) ACC ;\r
+__sfr __at (0xF0) B ;\r
+__sfr __at (0x81) SP ;\r
+__sfr __at (0x82) DPL ;\r
+__sfr __at (0x83) DPH ;\r
+//------------------\r
+__sfr __at (0xA2) AUXR1 ;\r
+__sfr __at (0xAC) CMP1 ;\r
+__sfr __at (0x95) DIVM ;\r
+\r
+__sfr __at (0xE7) FMADRH ;\r
+__sfr __at (0xE6) FMADRL ;\r
+__sfr __at (0xE4) FMCON ;\r
+__sfr __at (0xE5) FMDATA ;\r
+\r
+__sfr __at (0xA8) IEN0 ;\r
+__sfr __at (0xE8) IEN1 ;\r
+\r
+__sfr __at (0xB8) IP0 ;\r
+__sfr __at (0xB7) IP0H ;\r
+__sfr __at (0xF8) IP1 ;\r
+__sfr __at (0xF7) IP1H ;\r
+\r
+__sfr __at (0x94) KBCON ;\r
+__sfr __at (0x86) KBMASK ;\r
+__sfr __at (0x93) KBPATN ;\r
+\r
+__sfr __at (0x87) PCON ;\r
+__sfr __at (0xB5) PCONA ;\r
+__sfr __at (0xB6) PCONB ;\r
+\r
+__sfr __at (0xF6) PT0AD ;\r
+__sfr __at (0xDF) RSTSRC ;\r
+\r
+__sfr __at (0xD1) RTCCON ;\r
+__sfr __at (0xD2) RTCH ;\r
+__sfr __at (0xD3) RTCL ;\r
+\r
+__sfr __at (0x8F) TAMOD ;\r
+__sfr __at (0x88) TCON ;\r
+__sfr __at (0x8A) TL0 ;\r
+__sfr __at (0x8B) TL1 ;\r
+__sfr __at (0x8C) TH0 ;\r
+__sfr __at (0x8D) TH1 ;\r
+__sfr __at (0x89) TMOD ;\r
+__sfr __at (0x96) TRIM ;\r
+\r
+__sfr __at (0xA7) WDCON ;\r
+__sfr __at (0xC1) WDL ;\r
+__sfr __at (0xC2) WFEED1 ;\r
+__sfr __at (0xC3) WFEED2 ;\r
+\r
+\r
+/* BIT Registers */\r
+/* PSW */\r
+__sbit __at (0xD7) PSW_7;\r
+__sbit __at (0xD6) PSW_6;\r
+__sbit __at (0xD5) PSW_5;\r
+__sbit __at (0xD4) PSW_4;\r
+__sbit __at (0xD3) PSW_3;\r
+__sbit __at (0xD2) PSW_2;\r
+__sbit __at (0xD1) PSW_1;\r
+__sbit __at (0xD0) PSW_0;\r
+\r
+#define CY PSW_7\r
+#define AC PSW_6\r
+#define F0 PSW_5\r
+#define RS1 PSW_4\r
+#define RS0 PSW_3\r
+#define OV PSW_2\r
+#define F1 PSW_1\r
+#define P PSW_0\r
+\r
+/* TCON */\r
+__sbit __at (0x8F) TCON_7;\r
+__sbit __at (0x8E) TCON_6;\r
+__sbit __at (0x8D) TCON_5;\r
+__sbit __at (0x8C) TCON_4;\r
+\r
+#define TF1 TCON_7\r
+#define TR1 TCON_6\r
+#define TF0 TCON_5\r
+#define TR0 TCON_4\r
+\r
+/* IEN0 */\r
+__sbit __at (0xAF) IEN0_7;\r
+__sbit __at (0xAE) IEN0_6;\r
+__sbit __at (0xAD) IEN0_5;\r
+__sbit __at (0xAB) IEN0_3;\r
+__sbit __at (0xA9) IEN0_1;\r
+\r
+#define EA IEN0_7\r
+#define EWDRT IEN0_6\r
+#define EBO IEN0_5\r
+#define ET1 IEN0_3\r
+#define ET0 IEN0_1\r
+\r
+/* IEN1 */\r
+__sbit __at (0xEA) IEN1_2;\r
+__sbit __at (0xE9) IEN1_1;\r
+\r
+#define EC IEN1_2\r
+#define EKBI IEN1_1\r
+\r
+/* IP0 */\r
+__sbit __at (0xBE) IP0_6;\r
+__sbit __at (0xBD) IP0_5;\r
+__sbit __at (0xBB) IP0_3;\r
+__sbit __at (0xB9) IP0_1;\r
+\r
+#define PWDRT IP0_6\r
+#define PB0 IP0_5\r
+#define PT1 IP0_3\r
+#define PT0 IP0_1\r
+\r
+/* P0 */\r
+__sbit __at (0x85) P0_5;\r
+__sbit __at (0x84) P0_4;\r
+\r
+#define KB5 P0_5\r
+#define CMPREF P0_5\r
+#define KB4 P0_4\r
+#define CIN1A P0_4\r
+\r
+/* P1 */\r
+__sbit __at (0x95) P1_5;\r
+__sbit __at (0x92) P1_2;\r
+\r
+#define RST P1_5\r
+#define T0 P1_2\r
+\r
+/* P3 */\r
+__sbit __at (0xB1) P3_1;\r
+__sbit __at (0xB0) P3_0;\r
+\r
+#define XTAL1 P3_1\r
+#define XTAL2 P3_0\r
+\r
+#endif\r
projects / fw / sdcc / blobdiff