When attaching GDB to OpenOCD, the target state is no longer affected.

[fw/openocd] / TODO

diff --git a/TODO b/TODO
index ac43e2c7c0c6c8650d108ef5c8057f717b8ac6a0..283ed5f3a95e69fff4f59464967cd63460b992ce 100644 (file)
--- a/TODO
+++ b/TODO
@@ -114,6 +114,10 @@ Once the above are completed:
   https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html
 - regression: "reset halt" between 729(works) and 788(fails): @par
 https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
+- ARM7/9:
+  - add reset option to allow programming embedded ice while srst is asserted.
+  Some CPUs will gate the JTAG clock when srst is asserted and in this case,
+  it is necessary to program embedded ice and then assert srst afterwards.
 - ARM923EJS:
   - reset run/halt/step is not robust; needs testing to map out problems.
 - ARM11 improvements (MB?)
@@ -132,6 +136,10 @@ https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
   ARM1156 has Thumb2; ARM1136 doesn't.
 - Cortex A8 support (ML)
   - add target implementation (ML)
+- Generic ARM run_algorithm() interface
+  - tagged struct wrapping ARM instructions and metadata
+  - not revision-specific (current: ARMv4+ARMv5 -or- ARMv6 -or- ARMv7)
+  - usable with at least arm_nandwrite() and generic CFI drivers
 - MC1322x support (JW/DE?)
   - integrate and test support from JW (and DE?)
   - get working with a known good interface (i.e. not today's jlink)