+ Arc[278543 12795 11811 11811 600 2000 0 90 "clearline,lock"]
+ Arc[12795 121063 11811 11811 600 2000 180 90 "clearline,lock"]
+2013.01.25
+- reviewing design with an eye towards moving to production
+
+ - we have the ability to sample v_lipo, but is it useful?
+
+- need to move design to current preferred parts list
+- verify button fits cleanly through box wall
+- artwork is solid .. did a lot for v0.3
+
+2013.04.08
+- problems in v1.0 build fixed for v1.1
+ + companion and debug connectors should be rotated so cable dresses
+ towards center of board like TD
+ + update D1 footprint to clearly indicate cathode end so we don't
+ mess that up again
+ + we're not loading the flash part, so just remove it
+