- register names use "sp" not "r13"
- add top-level "mcr" and "mrc" commands, replacing
various core-specific operations
+ - basic semihosting support
ARM11
- Preliminary ETM and ETB hookup
- accelerated "flash erase_check"
- accelerated GDB memory checksum
- support "arm regs" command
- can access all core modes and registers
+ - watchpoint support
Cortex-A8
- support "arm regs" command
- can access all core modes and registers
- supports "reset-assert" event (used on OMAP3530)
+ - watchpoint support
Cortex-M3
- Exposed DWT registers like cycle counter