+ // FIFO
+ wire ch0_in, ch0_out, iq_out;
+ assign ch0_in = (phase == 1);
+
+ fifo_4k_18 rxfifo
+ ( // DSP Write Side
+ .data ( {ch0_in, phase[0], fifodata} ),
+ .wrreq (~rx_full & (phase != 0)),
+ .wrclk ( rxclk ),
+ .wrfull ( rx_full ),
+ .wrempty ( ),
+ .wrusedw ( ),
+ // USB Read Side
+ .q ( {ch0_out,iq_out,usbdata} ),
+ .rdreq ( RD & ~read_count[8] ),
+ .rdclk ( ~usbclk ),
+ .rdfull ( ),
+ .rdempty ( ),
+ .rdusedw ( rxfifolevel ),
+ // Async, shared
+ .aclr ( reset ) );
+
+ // DSP Write Side of FIFO
+ reg [15:0] ch_0_reg;
+ reg [15:0] ch_1_reg;
+ reg [15:0] ch_2_reg;
+ reg [15:0] ch_3_reg;
+ reg [15:0] ch_4_reg;
+ reg [15:0] ch_5_reg;
+ reg [15:0] ch_6_reg;
+ reg [15:0] ch_7_reg;
+