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Imported Upstream version 3.2.2
[debian/gnuradio]
/
usrp
/
fpga
/
sdr_lib
/
cic_interp.v
diff --git
a/usrp/fpga/sdr_lib/cic_interp.v
b/usrp/fpga/sdr_lib/cic_interp.v
index 0dd621623caf15ba7891276be588418c1fe25b82..32d106861afec242a3ef38ddd3c91a478a7dbb43 100755
(executable)
--- a/
usrp/fpga/sdr_lib/cic_interp.v
+++ b/
usrp/fpga/sdr_lib/cic_interp.v
@@
-45,11
+45,12
@@
module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
-
+
+ wire clear_me = reset | ~enable;
//FIXME Note that this section has pipe and diff reversed
// It still works, but is confusing
always @(posedge clock)
//FIXME Note that this section has pipe and diff reversed
// It still works, but is confusing
always @(posedge clock)
- if(
reset
)
+ if(
clear_me
)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable & strobe_out)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable & strobe_out)
@@
-61,7
+62,7
@@
module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_
end
always @(posedge clock)
end
always @(posedge clock)
- if(
reset
)
+ if(
clear_me
)
begin
for(i=0;i<N;i=i+1)
begin
begin
for(i=0;i<N;i=i+1)
begin
@@
-82,7
+83,8
@@
module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_
wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
- cic_int_shifter cic_int_shifter(rate,signal_out_unnorm,signal_out);
+ cic_int_shifter #(bw)
+ cic_int_shifter(rate,signal_out_unnorm,signal_out);
endmodule // cic_interp
endmodule // cic_interp