+N 62900 50800 62800 50800 4
+N 62800 49200 62800 50800 4
+N 62200 49600 62200 49800 4
+C 62000 50700 1 0 0 3.3V-plus-1.sym
+C 62300 49800 1 90 0 resistor.sym
+{
+T 61900 50100 5 10 0 0 90 0 1
+device=RESISTOR
+T 62000 50500 5 10 1 1 180 0 1
+refdes=R18
+T 62300 49795 5 10 0 1 90 0 1
+footprint=0402
+T 61700 50000 5 10 1 1 0 0 1
+value=10k
+T 62300 49800 5 10 0 1 0 0 1
+digikey=RMCF1/16S10K1%RCT-ND
+}
+T 61900 46700 9 10 1 0 0 0 4
+R18 shouldn't be necessary, but experience with
+a CP2103 GPIO interface to the debug port suggests
+we may need a stiff pullup. Consider 10k a placeholder
+for experimentation once we have real boards in hand.
+N 42400 69100 43700 69100 4
+{
+T 42400 69200 5 10 1 1 0 0 1
+netname=v_lipo
+}
+C 45900 51600 1 0 0 resistor-1.sym
+{
+T 46200 52000 5 10 0 0 0 0 1
+device=RESISTOR
+T 46200 52000 5 10 1 1 180 0 1
+refdes=R19
+T 46800 52000 5 10 1 1 180 0 1
+value=100
+T 45900 51600 5 10 0 0 90 0 1
+footprint=0402
+T 45900 51600 5 10 0 0 90 0 1
+digikey=P100JCT-ND
+}
+C 45900 49800 1 0 0 resistor-1.sym
+{
+T 46200 50200 5 10 0 0 0 0 1
+device=RESISTOR
+T 46200 50200 5 10 1 1 180 0 1
+refdes=R20
+T 46800 50200 5 10 1 1 180 0 1
+value=100
+T 45900 49800 5 10 0 0 90 0 1
+footprint=0402
+T 45900 49800 5 10 0 0 90 0 1
+digikey=P100JCT-ND
+}
+N 46800 51700 47200 51700 4
+N 46800 49900 47200 49900 4