+C 77100 56900 1 0 0 EMBEDDEDgnd.sym
+[
+P 77200 57000 77200 57200 1 0 1
+{
+T 77258 57061 5 4 0 1 0 0 1
+pinnumber=1
+T 77258 57061 5 4 0 0 0 0 1
+pinseq=1
+T 77258 57061 5 4 0 1 0 0 1
+pinlabel=1
+T 77258 57061 5 4 0 1 0 0 1
+pintype=pwr
+}
+L 77100 57000 77300 57000 3 0 0 0 -1 -1
+L 77155 56950 77245 56950 3 0 0 0 -1 -1
+L 77180 56910 77220 56910 3 0 0 0 -1 -1
+T 77400 56950 8 10 0 0 0 0 1
+net=GND:1
+]
+C 76400 56900 1 0 0 EMBEDDEDgnd.sym
+[
+P 76500 57000 76500 57200 1 0 1
+{
+T 76558 57061 5 4 0 1 0 0 1
+pinnumber=1
+T 76558 57061 5 4 0 0 0 0 1
+pinseq=1
+T 76558 57061 5 4 0 1 0 0 1
+pinlabel=1
+T 76558 57061 5 4 0 1 0 0 1
+pintype=pwr
+}
+L 76400 57000 76600 57000 3 0 0 0 -1 -1
+L 76455 56950 76545 56950 3 0 0 0 -1 -1
+L 76480 56910 76520 56910 3 0 0 0 -1 -1
+T 76700 56950 8 10 0 0 0 0 1
+net=GND:1
+]
+C 69500 51800 1 0 0 EMBEDDEDCC1200.sym
+[
+P 69500 55200 69900 55200 1 0 0
+{
+T 69600 55300 5 10 1 1 0 0 1
+pinnumber=9
+T 70000 55200 3 10 1 1 0 0 1
+pinlabel=SO/GPIO1
+T 69100 55300 5 10 0 1 0 0 1
+pinseq=9
+T 69500 55200 5 10 0 1 0 0 1
+pintype=io
+}
+P 69500 54800 69900 54800 1 0 0
+{
+T 69600 54900 5 10 1 1 0 0 1
+pinnumber=10
+T 70000 54800 3 10 1 1 0 0 1
+pinlabel=GPIO0
+T 69100 54900 5 10 0 1 0 0 1
+pinseq=10
+T 69500 54800 5 10 0 1 0 0 1
+pintype=io
+}
+P 69500 52400 69900 52400 1 0 0
+{
+T 69805 52445 5 10 1 1 0 6 1
+pinnumber=16
+T 69955 52395 3 10 1 1 0 0 1
+pinlabel=NC
+T 69500 52400 5 10 0 1 180 0 1
+pinseq=16
+T 69500 52400 5 10 0 1 180 0 1
+pintype=io
+}
+P 69500 52800 69900 52800 1 0 0
+{
+T 69805 52845 5 10 1 1 0 6 1
+pinnumber=15
+T 69955 52795 3 10 1 1 0 0 1
+pinlabel=AVDD_RF
+T 69500 52800 5 10 0 1 180 0 1
+pinseq=15
+T 69500 52800 5 10 0 1 180 0 1
+pintype=pwr
+}
+P 73100 53600 72700 53600 1 0 0
+{
+T 72800 53700 5 10 1 1 0 0 1
+pinnumber=20
+T 72000 53600 3 10 1 1 0 0 1
+pinlabel=LNA_N
+T 73100 53600 5 10 0 1 0 0 1
+pinseq=20
+T 73100 53600 5 10 0 1 0 0 1
+pintype=io
+}
+P 73100 53200 72700 53200 1 0 0
+{
+T 72025 53200 3 10 1 1 0 0 1
+pinlabel=LNA_P
+T 73100 53200 5 10 0 1 0 0 1
+pinseq=19
+T 72800 53300 5 10 1 1 0 0 1
+pinnumber=19
+T 73100 53200 5 10 0 1 0 0 1
+pintype=io
+}
+P 73100 52800 72700 52800 1 0 0
+{
+T 72800 52900 5 10 1 1 0 0 1
+pinnumber=18
+T 71825 52800 3 10 1 1 0 0 1
+pinlabel=TRX_SW
+T 73100 52800 5 10 0 1 0 0 1
+pinseq=18
+T 73100 52800 5 10 0 1 0 0 1
+pintype=io
+}
+P 73100 52400 72700 52400 1 0 0
+{
+T 72800 52500 5 10 1 1 0 0 1
+pinnumber=17
+T 72325 52400 3 10 1 1 0 0 1
+pinlabel=PA
+T 73100 52400 5 10 0 1 0 0 1
+pinseq=17
+T 73100 52400 5 10 0 1 0 0 1
+pintype=io
+}
+P 73100 55200 72700 55200 1 0 0
+{
+T 72800 55300 5 10 1 1 0 0 1
+pinnumber=24
+T 72125 55200 3 10 1 1 0 0 1
+pinlabel=LPF1
+T 73100 55200 5 10 0 1 0 0 1
+pinseq=24
+T 73100 55200 5 10 0 1 0 0 1
+pintype=io
+}
+P 73100 54800 72700 54800 1 0 0
+{
+T 72800 54900 5 10 1 1 0 0 1
+pinnumber=23
+T 72100 54800 3 10 1 1 0 0 1
+pinlabel=LPF0
+T 73100 54800 5 10 0 1 0 0 1
+pinseq=23
+T 73100 54800 5 10 0 1 0 0 1
+pintype=io
+}
+P 73100 54400 72700 54400 1 0 0
+{
+T 72800 54500 5 10 1 1 0 0 1
+pinnumber=22
+T 71250 54400 3 10 1 1 0 0 1
+pinlabel=AVDD_SYNTH1
+T 73100 54400 5 10 0 1 0 0 1
+pinseq=22
+T 73100 54400 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 73100 54000 72700 54000 1 0 0
+{
+T 72800 54100 5 10 1 1 0 0 1
+pinnumber=21
+T 71600 54000 3 10 1 1 0 0 1
+pinlabel=DCPL_VCO
+T 73100 54000 5 10 0 1 0 0 1
+pinseq=21
+T 73100 54000 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 69500 53200 69900 53200 1 0 0
+{
+T 69805 53245 5 10 1 1 0 6 1
+pinnumber=14
+T 69955 53195 3 10 1 1 0 0 1
+pinlabel=RBIAS
+T 69100 53300 5 10 0 1 0 0 1
+pinseq=14
+T 69500 53200 5 10 0 1 0 0 1
+pintype=io
+}
+P 69500 55600 69900 55600 1 0 0
+{
+T 69600 55700 5 10 1 1 0 0 1
+pinnumber=8
+T 70000 55600 3 10 1 1 0 0 1
+pinlabel=SCLK
+T 69600 55700 5 10 1 1 0 0 1
+pinseq=8
+T 69500 55600 5 10 0 1 0 0 1
+pintype=in
+}
+P 69500 58400 69900 58400 1 0 0
+{
+T 69600 58500 5 10 1 1 0 0 1
+pinnumber=1
+T 70000 58400 3 10 1 1 0 0 1
+pinlabel=VDD_GUARD
+T 69100 58500 5 10 0 1 0 0 1
+pinseq=1
+T 69500 58400 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 69500 58000 69900 58000 1 0 0
+{
+T 69600 58100 5 10 1 1 0 0 1
+pinnumber=2
+T 70000 58000 3 10 1 1 0 0 1
+pinlabel=RESET_N
+T 69100 58100 5 10 0 1 0 0 1
+pinseq=2
+T 69500 58000 5 10 0 1 0 0 1
+pintype=in
+}
+P 69500 57600 69900 57600 1 0 0
+{
+T 69600 57700 5 10 1 1 0 0 1
+pinnumber=3
+T 70000 57600 3 10 1 1 0 0 1
+pinlabel=GPIO3
+T 69100 57700 5 10 0 1 0 0 1
+pinseq=3
+T 69500 57600 5 10 0 1 0 0 1
+pintype=io
+}
+P 69500 57200 69900 57200 1 0 0
+{
+T 69600 57300 5 10 1 1 0 0 1
+pinnumber=4
+T 70000 57200 3 10 1 1 0 0 1
+pinlabel=GPIO2
+T 69100 57300 5 10 0 1 0 0 1
+pinseq=4
+T 69500 57200 5 10 0 1 0 0 1
+pintype=io
+}
+P 69500 56800 69900 56800 1 0 0
+{
+T 69600 56900 5 10 1 1 0 0 1
+pinnumber=5
+T 70000 56800 3 10 1 1 0 0 1
+pinlabel=DVDD
+T 69100 56900 5 10 0 1 0 0 1
+pinseq=5
+T 69500 56800 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 69500 56400 69900 56400 1 0 0
+{
+T 69600 56500 5 10 1 1 0 0 1
+pinnumber=6
+T 70000 56400 3 10 1 1 0 0 1
+pinlabel=DCPL
+T 69100 56500 5 10 0 1 0 0 1
+pinseq=6
+T 69500 56400 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 69500 56000 69900 56000 1 0 0
+{
+T 69600 56100 5 10 1 1 0 0 1
+pinnumber=7
+T 70000 56000 3 10 1 1 0 0 1
+pinlabel=SI
+T 69100 56100 5 10 0 1 0 0 1
+pinseq=7
+T 69500 56000 5 10 0 1 0 0 1
+pintype=in
+}
+P 69500 54400 69900 54400 1 0 0
+{
+T 69600 54500 5 10 1 1 0 0 1
+pinnumber=11
+T 70000 54400 3 10 1 1 0 0 1
+pinlabel=CS_N
+T 69000 54300 5 10 0 1 0 0 1
+pinseq=11
+T 69500 54400 5 10 0 1 0 0 1
+pintype=in
+}
+P 69500 54000 69900 54000 1 0 0
+{
+T 69600 54100 5 10 1 1 0 0 1
+pinnumber=12
+T 70000 54000 3 10 1 1 0 0 1
+pinlabel=DVDD
+T 69100 54100 5 10 0 1 0 0 1
+pinseq=12
+T 69500 54000 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 69500 53600 69900 53600 1 0 0
+{
+T 69805 53645 5 10 1 1 0 6 1
+pinnumber=13
+T 69955 53595 3 10 1 1 0 0 1
+pinlabel=AVDD_IF
+T 69100 53700 5 10 0 1 0 0 1
+pinseq=13
+T 69500 53600 5 10 0 1 0 0 1
+pintype=pwr
+}
+B 69900 51800 2800 6900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 74900 53400 8 10 0 0 0 0 1
+description=TI CC1200 Low Power, High Performance RF Transceiver
+T 69900 58800 8 10 0 1 0 0 1
+refdes=U?
+T 72300 59100 9 10 0 1 0 0 1
+device=IC
+T 72000 58800 9 10 0 1 0 0 1
+value=CC1200
+P 73100 56800 72700 56800 1 0 0
+{
+T 72800 56900 5 10 1 1 0 0 1
+pinnumber=28
+T 71500 56800 3 10 1 1 0 0 1
+pinlabel=AVDD_XOSC
+T 73100 56800 5 10 0 1 0 0 1
+pinseq=28
+T 73100 56800 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 73100 56400 72700 56400 1 0 0
+{
+T 71275 56400 3 10 1 1 0 0 1
+pinlabel=AVDD_SYNTH2
+T 73100 56400 5 10 0 1 0 0 1
+pinseq=27
+T 72800 56500 5 10 1 1 0 0 1
+pinnumber=27
+T 73100 56400 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 73100 56000 72700 56000 1 0 0
+{
+T 72800 56100 5 10 1 1 0 0 1
+pinnumber=26
+T 71175 56000 3 10 1 1 0 0 1
+pinlabel=DCPL_PFD_CHP
+T 73100 56000 5 10 0 1 0 0 1
+pinseq=26
+T 73100 56000 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 73100 55600 72700 55600 1 0 0
+{
+T 72800 55700 5 10 1 1 0 0 1
+pinnumber=25
+T 71175 55600 3 10 1 1 0 0 1
+pinlabel=AVDD_PFD_CHP
+T 73100 55600 5 10 0 1 0 0 1
+pinseq=25
+T 73100 55600 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 73100 58400 72700 58400 1 0 0
+{
+T 72800 58500 5 10 1 1 0 0 1
+pinnumber=32
+T 71625 58400 3 10 1 1 0 0 1
+pinlabel=EXT_XOSC
+T 73100 58400 5 10 0 1 0 0 1
+pinseq=32
+T 73100 58400 5 10 0 1 0 0 1
+pintype=in
+}
+P 73100 58000 72700 58000 1 0 0
+{
+T 72800 58100 5 10 1 1 0 0 1
+pinnumber=31
+T 71750 58000 3 10 1 1 0 0 1
+pinlabel=XOSC_Q2
+T 73100 58000 5 10 0 1 0 0 1
+pinseq=31
+T 73100 58000 5 10 0 1 0 0 1
+pintype=io
+}
+P 73100 57600 72700 57600 1 0 0
+{
+T 72800 57700 5 10 1 1 0 0 1
+pinnumber=30
+T 71750 57600 3 10 1 1 0 0 1
+pinlabel=XOSC_Q1
+T 73100 57600 5 10 0 1 0 0 1
+pinseq=30
+T 73100 57600 5 10 0 1 0 0 1
+pintype=io
+}
+P 73100 57200 72700 57200 1 0 0
+{
+T 72800 57300 5 10 1 1 0 0 1
+pinnumber=29
+T 71500 57200 3 10 1 1 0 0 1
+pinlabel=DCPL_XOSC
+T 73100 57200 5 10 0 1 0 0 1
+pinseq=29
+T 73100 57200 5 10 0 1 0 0 1
+pintype=pwr
+}
+P 73100 52000 72700 52000 1 0 0
+{
+T 72800 52100 5 10 1 1 0 0 1
+pinnumber=33
+T 72125 52000 3 10 1 1 0 0 1
+pinlabel=GND
+T 73100 52000 5 10 0 1 0 0 1
+pinseq=32
+T 73100 52000 5 10 0 1 0 0 1
+pintype=in
+}
+]