+N 81700 49800 82800 49800 4
+{
+T 82100 49900 5 10 1 1 0 0 1
+netname=bt_p2_0
+}
+N 69700 48100 70900 48100 4
+{
+T 70200 48200 5 10 1 1 0 0 1
+netname=bt_p2_0
+}
+N 53900 42200 55100 42200 4
+{
+T 54400 42300 5 10 1 1 0 0 1
+netname=bt_rst_n
+}
+C 75200 49300 1 90 0 resistor.sym
+{
+T 74800 49600 5 10 0 0 90 0 1
+device=RESISTOR
+T 75200 49300 5 10 0 1 90 0 1
+footprint=0402
+T 74900 50000 5 10 1 1 180 0 1
+refdes=R6
+T 74900 49700 5 10 1 1 180 0 1
+value=56k
+}
+C 75000 49000 1 0 0 gnd.sym
+N 81700 48200 82800 48200 4
+{
+T 82000 48300 5 10 1 1 0 0 1
+netname=bt_p0_4
+}
+N 69700 50100 70900 50100 4
+{
+T 70200 50200 5 10 1 1 0 0 1
+netname=bt_p0_4
+}
+N 75500 46600 76700 46600 4
+{
+T 75500 46700 5 10 1 1 0 0 1
+netname=bt_p1_5
+}
+N 75500 47000 76700 47000 4
+{
+T 75500 47100 5 10 1 1 0 0 1
+netname=bt_p0_5
+}
+N 75500 46200 76700 46200 4
+{
+T 75500 46300 5 10 1 1 0 0 1
+netname=bt_p1_2
+}
+N 69700 46900 70900 46900 4
+{
+T 70200 47000 5 10 1 1 0 0 1
+netname=bt_p1_5
+}
+N 69700 47300 70900 47300 4
+{
+T 70200 47400 5 10 1 1 0 0 1
+netname=bt_p0_5
+}
+N 69700 46500 70900 46500 4
+{
+T 70200 46600 5 10 1 1 0 0 1
+netname=bt_p1_2
+}
+N 75500 43400 76700 43400 4
+{
+T 75500 43500 5 10 1 1 0 0 1
+netname=bt_p3_6
+}
+N 69700 44100 70900 44100 4
+{
+T 70200 44200 5 10 1 1 0 0 1
+netname=bt_p3_6
+}
+N 81700 49400 82800 49400 4
+{
+T 82100 49500 5 10 1 1 0 0 1
+netname=bt_sw_btn
+}
+N 81700 49000 82800 49000 4
+{
+T 82100 49100 5 10 1 1 0 0 1
+netname=bt_wake_up
+}
+N 81700 48600 82800 48600 4
+{
+T 82100 48700 5 10 1 1 0 0 1
+netname=bt_p2_4
+}
+N 60000 52800 61300 52800 4
+{
+T 60000 52900 5 10 1 1 0 0 1
+netname=bt_sw_btn
+}
+N 69700 45700 70900 45700 4
+{
+T 70200 45800 5 10 1 1 0 0 1
+netname=bt_wake_up
+}
+N 53000 45300 54200 45300 4
+{
+T 53000 45400 5 10 1 1 0 0 1
+netname=bt_p2_4
+}
+N 81700 50600 82800 50600 4
+{
+T 82100 50700 5 10 1 1 0 0 1
+netname=bt_p3_7
+}
+N 69700 44500 70900 44500 4
+{
+T 70200 44600 5 10 1 1 0 0 1
+netname=bt_p3_7
+}
+N 54200 43300 53900 43300 4
+N 53900 43300 53900 42200 4
+N 62400 51200 62400 51600 4
+N 62400 51600 61600 51600 4
+N 61600 51600 61600 54100 4
+N 62000 51200 61300 51200 4
+N 61300 51200 61300 52800 4
+C 76700 43200 1 0 0 RN4678.sym
+{
+T 77100 51400 5 10 1 1 0 0 1
+refdes=U3
+T 79895 51400 5 10 1 1 0 0 1
+value=RN4678
+T 77095 51800 5 10 0 0 0 0 1
+footprint=RN4678
+T 76700 43200 5 10 0 1 0 0 1
+device=IC
+}
+N 82100 47400 82100 47000 4
+N 81700 47400 82100 47400 4
+N 82100 47000 81700 47000 4
+T 77100 40800 9 10 1 0 0 0 2
+ Copyright 2017 by Bdale Garbee <bdale@gag.com>
+Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
+C 76200 45700 1 0 0 nc-left.sym
+{
+T 76200 46100 5 10 0 0 0 0 1
+value=NoConnection
+T 76200 46500 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 69700 46000 1 0 0 nc-right.sym
+{
+T 69800 46500 5 10 0 0 0 0 1
+value=NoConnection
+T 69800 46700 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 69700 47600 1 0 0 nc-right.sym
+{
+T 69800 48100 5 10 0 0 0 0 1
+value=NoConnection
+T 69800 48300 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 69700 48800 1 0 0 nc-right.sym
+{
+T 69800 49300 5 10 0 0 0 0 1
+value=NoConnection
+T 69800 49500 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 53700 45600 1 0 0 nc-left.sym
+{
+T 53700 46000 5 10 0 0 0 0 1
+value=NoConnection
+T 53700 46400 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 81700 50900 1 0 0 nc-right.sym
+{
+T 81800 51400 5 10 0 0 0 0 1
+value=NoConnection
+T 81800 51600 5 10 0 0 0 0 1
+device=DRC_Directive
+}