+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+ target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+
+ $_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+ flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+ flash bank $_CHIPNAME.otp.cpu1 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1
+
+ if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+ }
+
+ proc stm32wlx_wkup_cm0p {} {
+ set _CHIPNAME [stm32wlx_get_chipname]
+
+ # enable CPU2 boot after reset and after wakeup from Stop or Standby mode
+ # PWR_CR4 |= C2BOOT
+ stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0
+ }
+}
+
+# get _CHIPNAME from current target
+proc stm32wlx_get_chipname {} {
+ set t [target current]
+ set sep [string last "." $t]
+ if {$sep == -1} {
+ return $t
+ }
+ return [string range $t 0 [expr $sep - 1]]
+}
+
+# like mrw, but with target selection
+proc stm32wlx_mrw {used_target reg} {
+ set value ""
+ $used_target mem2array value 32 $reg 1
+ return $value(0)
+}
+
+# like mmw, but with target selection
+proc stm32wlx_mmw {used_target reg setbits clearbits} {
+ set old [stm32wlx_mrw $used_target $reg]
+ set new [expr {($old & ~$clearbits) | $setbits}]
+ $used_target mww $reg $new
+}
+
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate