+proc proc_post_enable {_chipname} {
+ targets $_chipname.cpu
+
+ if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+ switch [$_chipname.tpiu cget -port-width] {
+ 1 {
+ mmw 0xE0042004 0x00000060 0x000000c0
+ mmw 0x48001020 0x00000000 0x0000ff00
+ mmw 0x48001000 0x000000a0 0x000000f0
+ mmw 0x48001008 0x000000f0 0x00000000
+ }
+ 2 {
+ mmw 0xE0042004 0x000000a0 0x000000c0
+ mmw 0x48001020 0x00000000 0x000fff00
+ mmw 0x48001000 0x000002a0 0x000003f0
+ mmw 0x48001008 0x000003f0 0x00000000
+ }
+ 4 {
+ mmw 0xE0042004 0x000000e0 0x000000c0
+ mmw 0x48001020 0x00000000 0x0fffff00
+ mmw 0x48001000 0x00002aa0 0x00003ff0
+ mmw 0x48001008 0x00003ff0 0x00000000
+ }
+ }
+ } else {
+ mmw 0xE0042004 0x00000020 0x000000c0
+ }
+}
+
+$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
+