+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
+ targets $_chipname.cpu
+
+ if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+ switch [$_chipname.tpiu cget -port-width] {
+ 1 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
+ mmw 0xE0042004 0x00000060 0x000000c0
+ mmw 0x48001020 0x00000000 0x0000ff00
+ mmw 0x48001000 0x000000a0 0x000000f0
+ mmw 0x48001008 0x000000f0 0x00000000
+ }
+ 2 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
+ mmw 0xE0042004 0x000000a0 0x000000c0
+ mmw 0x48001020 0x00000000 0x000fff00
+ mmw 0x48001000 0x000002a0 0x000003f0
+ mmw 0x48001008 0x000003f0 0x00000000
+ }
+ 4 {
+ # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
+ mmw 0xE0042004 0x000000e0 0x000000c0
+ mmw 0x48001020 0x00000000 0x0fffff00
+ mmw 0x48001000 0x00002aa0 0x00003ff0
+ mmw 0x48001008 0x00003ff0 0x00000000
+ }
+ }
+ } else {
+ # Set TRACE_IOEN; TRACE_MODE to async
+ mmw 0xE0042004 0x00000020 0x000000c0
+ }
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
+
+$_TARGETNAME configure -event reset-init {
+ # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
+ # Use MSI 24 MHz clock, compliant even with VOS == 2.
+ # 3 WS compliant with VOS == 2 and 24 MHz.
+ mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
+ mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
+
+ # Boost JTAG frequency
+ adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+ # Reset clock is MSI (4 MHz)
+ adapter speed 500