+
+if {[set $_CHIPNAME.USE_CTI]} {
+ # create CTI instances for both cores
+ cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
+ cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
+
+ $_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
+ $_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
+
+ $_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+ $_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+
+ proc stm32h7x_cti_start {} {
+ set _CHIPNAME [stm32h7x_get_chipname]
+
+ # Configure Cores' CTIs to halt each other
+ # TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
+ $_CHIPNAME.cti0 write INEN0 0x1
+ $_CHIPNAME.cti0 write OUTEN0 0x1
+ $_CHIPNAME.cti1 write INEN0 0x1
+ $_CHIPNAME.cti1 write OUTEN0 0x1
+
+ # enable CTIs
+ $_CHIPNAME.cti0 enable on
+ $_CHIPNAME.cti1 enable on
+ }
+
+ proc stm32h7x_cti_stop {} {
+ set _CHIPNAME [stm32h7x_get_chipname]
+
+ $_CHIPNAME.cti0 enable off
+ $_CHIPNAME.cti1 enable off
+ }
+
+ proc stm32h7x_cti_prepare_restart_all {} {
+ stm32h7x_cti_prepare_restart cti0
+ stm32h7x_cti_prepare_restart cti1
+ }
+
+ proc stm32h7x_cti_prepare_restart {cti} {
+ set _CHIPNAME [stm32h7x_get_chipname]
+
+ # Acknowlodge EDBGRQ at TRIGOUT0
+ $_CHIPNAME.$cti write INACK 0x01
+ $_CHIPNAME.$cti write INACK 0x00
+ }
+}