+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+proc stm32f0x_default_reset_start {} {
+ # Reset clock is HSI (8 MHz)
+ adapter speed 1000
+}
+
+proc stm32f0x_default_examine_end {} {
+ # Enable debug during low power modes (uses more power)
+ mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+
+ # Stop watchdog counters during halt
+ mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f0x_default_reset_init {} {
+ # Configure PLL to boost clock to HSI x 6 (48 MHz)
+ mww 0x40021004 0x00100000 ;# RCC_CFGR = PLLMUL[2]
+ mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
+ mww 0x40022000 0x00000011 ;# FLASH_ACR = PRFTBE | LATENCY[0]
+ sleep 10 ;# Wait for PLL to lock
+ mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+ # Boost JTAG frequency
+ adapter speed 8000
+}