-# JTAG clock should be CCLK/6 (unless using adaptive clocking)
-# CCLK is 4 MHz after reset, and until board-specific code (like
-# a reset-init handler) speeds it up.
-#
-# Although rclk "appears to work", it turns out that this yields
-# 4MHz whereas the "correct" rate is CCLK/6, which is not what
-# you get with rclk.
-jtag_khz [ expr 4000 / 6 ]
-
-
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+jtag_khz 10