+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# The Atheros AR9331 is a highly integrated and cost effective
+# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless
+# local area network (WLAN) AP and router platforms.
+#
+# Notes:
+# - MIPS Processor ID (PRId): 0x00019374
+# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
+# operating at up to 400 MHz
+# - External 16-bit DDR1, DDR2, or SDRAM memory interface
+# - TRST is not available.
+# - EJTAG PrRst signal is not supported
+# - RESET_L pin A72 on the SoC will reset internal JTAG logic.
+#
+
+# Pins related for debug and bootstrap:
+# Name Pin Description
+# JTAG
+# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG
+# JTAG_TDI GPIO6, (B46) Software configurable, default JTAG
+# JTAG_TDO GPIO7, (A54) Software configurable, default JTAG
+# JTAG_TMS GPIO8, (A52) Software configurable, default JTAG
+# Reset
+# RESET_L -, (A72) Input only
+# SYS_RST_L ???????? Output reset request or GPIO
+# Bootstrap
+# MEM_TYPE[1] GPIO28, (A74) 0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM
+# MEM_TYPE[0] GPIO12, (A56)
+# FW_DOWNLOAD GPIO16, (A75) Used if BOOT_FROM_SPI = 0. 0 - boot from USB
+# 1 - boot from MDIO.
+# JTAG_MODE(JS) GPIO11, (B48) 0 - JTAG (Default); 1 - EJTAG
+# BOOT_FROM_SPI GPIO1, (A77) 0 - ROM boot; 1 - SPI boot
+# SEL_25M_40M GPIO0, (A78) 0 - 25MHz; 1 - 40MHz
+# UART
+# UART0_SOUT GPIO10, (A79)
+# UART0_SIN GPIO9, (B68)
+
+# Per default we need to use "none" variant to be able properly "reset init"
+# or "reset halt" the CPU.
+reset_config none srst_pulls_trst
+
+# For SRST based variant we still need proper timings.
+# For ETH part the reset should be asserted at least for 10ms
+# Since there is no other information let's take 100ms to be sure.
+adapter srst pulse_width 100
+
+# according to the SoC documentation it should take at least 5ms from
+# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
+# to live.
+adapter srst delay 8
+