-
- # at reset chip runs at 32khz
- jtag_khz 8
- halt
- mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
-
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
- sleep 10 # wait 10 ms
- mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
- sleep 10 # wait 10 ms
+ mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
+
+ mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
+ sleep 10 ;# wait 10 ms