- mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0)
- mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8)
-
- mww 0xb8000010 8 # force precharge all banks
- mww 0xb8000010 1 # force EMRS update cycle
- mww 0xb800000c 0 # clr ext. mode register
- mww 0xb8000010 2 # force auto refresh all banks
- mww 0xb8000010 8 # force precharge all banks
- mww 0xb8000008 0x31 # set DDR mode value CAS=3
- mww 0xb8000010 1 # force EMRS update cycle
- mww 0xb8000014 0x461b # DDR refresh value
- mww 0xb8000018 0xffff # DDR Read Data This Cycle value (16bit: 0xffff)
- mww 0xb800001c 0x7 # delay added to the DQS line (normal = 7)
+ mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0)
+ mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8)
+
+ mww 0xb8000010 8 ;# force precharge all banks
+ mww 0xb8000010 1 ;# force EMRS update cycle
+ mww 0xb800000c 0 ;# clr ext. mode register
+ mww 0xb8000010 2 ;# force auto refresh all banks
+ mww 0xb8000010 8 ;# force precharge all banks
+ mww 0xb8000008 0x31 ;# set DDR mode value CAS=3
+ mww 0xb8000010 1 ;# force EMRS update cycle
+ mww 0xb8000014 0x461b ;# DDR refresh value
+ mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff)
+ mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7)