-set REVISION_PRM [expr $PRCM_BASE_ADDR + 0x0000]
-set PRM_IRQSTATUS_MPU [expr $PRCM_BASE_ADDR + 0x0004]
-set PRM_IRQENABLE_MPU [expr $PRCM_BASE_ADDR + 0x0008]
-set PRM_IRQSTATUS_M3 [expr $PRCM_BASE_ADDR + 0x000c]
-set PRM_IRQENABLE_M3 [expr $PRCM_BASE_ADDR + 0x0010]
-set PM_MPU_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0300]
-set PM_MPU_PWRSTST [expr $PRCM_BASE_ADDR + 0x0304]
-set RM_MPU_RSTST [expr $PRCM_BASE_ADDR + 0x0314]
-set RM_MPU_CONTEXT [expr $PRCM_BASE_ADDR + 0x0324]
-set PM_GFX_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0400]
-set PM_GFX_PWRSTST [expr $PRCM_BASE_ADDR + 0x0404]
-set RM_GFX_RSTCTRL [expr $PRCM_BASE_ADDR + 0x0410]
-set RM_GFX_RSTST [expr $PRCM_BASE_ADDR + 0x0414]
-set RM_GFX_CONTEXT [expr $PRCM_BASE_ADDR + 0x0424]
-set RM_RTC_CONTEXT [expr $PRCM_BASE_ADDR + 0x0524]
-set RM_WKUP_RSTCTRL [expr $PRCM_BASE_ADDR + 0x2010]
-set RM_WKUP_RSTST [expr $PRCM_BASE_ADDR + 0x2014]
-set CM_L3_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2800]
-set CM_WKUP_DEBUGSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2820]
-set CM_L3S_TSC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2900]
-set CM_WKUP_ADC_TSC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2920]
-set CM_L4_WKUP_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2a00]
-set CM_WKUP_L4WKUP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a20]
-set CM_WKUP_WKUP_M3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a28]
-set CM_WKUP_SYNCTIMER_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a30]
-set CM_WKUP_CLKDIV32K_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a38]
-set CM_WKUP_USBPHY0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a40]
-set CM_WKUP_USBPHY1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a48]
-set CM_WKUP_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2b00]
-set CM_WKUP_TIMER0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b20]
-set CM_WKUP_TIMER1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b28]
-set CM_WKUP_WDT0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b30]
-set CM_WKUP_WDT1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b38]
-set CM_WKUP_I2C0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b40]
-set CM_WKUP_UART0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b48]
-set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b50]
-set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b58]
-set CM_WKUP_CONTROL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b60]
-set CM_WKUP_GPIO0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b68]
-set CM_CLKMODE_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d20]
-set CM_IDLEST_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d24]
-set CM_CLKSEL_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d2c]
-set CM_DIV_M4_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d38]
-set CM_DIV_M5_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d3c]
-set CM_DIV_M6_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d40]
-set CM_SSC_DELTAMSTEP_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d48]
-set CM_SSC_MODFREQDIV_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d4c]
-set CM_CLKMODE_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d60]
-set CM_IDLEST_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d64]
-set CM_CLKSEL_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d6c]
-set CM_DIV_M2_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d70]
-set CM_SSC_DELTAMSTEP_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d88]
-set CM_SSC_MODFREQDIV_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d8c]
-set CM_CLKMODE_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da0]
-set CM_IDLEST_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da4]
-set CM_CLKSEL_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dac]
-set CM_DIV_M2_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db0]
-set CM_DIV_M4_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db8]
-set CM_SSC_DELTAMSTEP_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dc8]
-set CM_SSC_MODFREQDIV_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dcc]
-set CM_CLKMODE_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de0]
-set CM_IDLEST_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de4]
-set CM_CLKSEL_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2dec]
-set CM_DIV_M2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2df0]
-set CM_CLKSEL2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e04]
-set CM_SSC_DELTAMSTEP_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e08]
-set CM_SSC_MODFREQDIV_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e0c]
-set CM_CLKDCOLDO_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e14]
-set CM_CLKMODE_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e20]
-set CM_IDLEST_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e24]
-set CM_CLKSEL_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e2c]
-set CM_DIV_M2_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e30]
-set CM_SSC_DELTAMSTEP_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e48]
-set CM_SSC_MODFREQDIV_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e4c]
-set CM_CLKMODE_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e60]
-set CM_IDLEST_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e64]
-set CM_CLKSEL_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e6c]
-set CM_DIV_M2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e70]
-set CM_CLKSEL2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e84]
-set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e88]
-set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e8c]
-set CM_SHADOW_FREQ_CONFIG1 [expr $PRCM_BASE_ADDR + 0x2fa0]
-set CM_SHADOW_FREQ_CONFIG2 [expr $PRCM_BASE_ADDR + 0x2fa4]
-set CM_CLKOUT1_CTRL [expr $PRCM_BASE_ADDR + 0x4100]
-set CM_DLL_CTRL [expr $PRCM_BASE_ADDR + 0x4104]
-set CM_CLKOUT2_CTRL [expr $PRCM_BASE_ADDR + 0x4108]
-set CLKSEL_TIMER1MS_CLK [expr $PRCM_BASE_ADDR + 0x4200]
-set CLKSEL_TIMER2_CLK [expr $PRCM_BASE_ADDR + 0x4204]
-set CLKSEL_TIMER3_CLK [expr $PRCM_BASE_ADDR + 0x4208]
-set CLKSEL_TIMER4_CLK [expr $PRCM_BASE_ADDR + 0x420c]
-set CLKSEL_TIMER5_CLK [expr $PRCM_BASE_ADDR + 0x4210]
-set CLKSEL_TIMER6_CLK [expr $PRCM_BASE_ADDR + 0x4214]
-set CLKSEL_TIMER7_CLK [expr $PRCM_BASE_ADDR + 0x4218]
-set CLKSEL_TIMER8_CLK [expr $PRCM_BASE_ADDR + 0x421c]
-set CLKSEL_TIMER9_CLK [expr $PRCM_BASE_ADDR + 0x4220]
-set CLKSEL_TIMER10_CLK [expr $PRCM_BASE_ADDR + 0x4224]
-set CLKSEL_TIMER11_CLK [expr $PRCM_BASE_ADDR + 0x4228]
-set CLKSEL_WDT1_CLK [expr $PRCM_BASE_ADDR + 0x422c]
-set CLKSEL_SYNCTIMER_CLK [expr $PRCM_BASE_ADDR + 0x4230]
-set CLKSEL_MAC_CLK [expr $PRCM_BASE_ADDR + 0x4234]
-set CLKSEL_CPTS_RFT_CLK [expr $PRCM_BASE_ADDR + 0x4238]
-set CLKSEL_GFX_FCLK [expr $PRCM_BASE_ADDR + 0x423c]
-set CLKSEL_GPIO0_DBCLK [expr $PRCM_BASE_ADDR + 0x4240]
-set CLKSEL_LCDC_PIXEL_CLK [expr $PRCM_BASE_ADDR + 0x4244]
-set CLKSEL_ICSS_OCP_CLK [expr $PRCM_BASE_ADDR + 0x4248]
-set CLKSEL_DLL_AGING_CLK [expr $PRCM_BASE_ADDR + 0x4250]
-set CLKSEL_USBPHY32KHZ_GCLK [expr $PRCM_BASE_ADDR + 0x4260]
-set CM_MPU_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8300]
-set CM_MPU_MPU_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8320]
-set CM_GFX_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8400]
-set CM_GFX_GFX_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8420]
-set CM_RTC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8500]
-set CM_RTC_RTC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8520]
-set CM_PER_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8800]
-set CM_PER_L3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8820]
-set CM_PER_AES0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8828]
-set CM_PER_DES_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8830]
-set CM_PER_CRYPTODMA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8838]
-set CM_PER_L3_INSTR_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8840]
-set CM_PER_MSTR_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8848]
-set CM_PER_OCMCRAM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8850]
-set CM_PER_SHA0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8858]
-set CM_PER_SLV_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8860]
-set CM_PER_VPFE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8868]
-set CM_PER_VPFE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8870]
-set CM_PER_TPCC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8878]
-set CM_PER_TPTC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8880]
-set CM_PER_TPTC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8888]
-set CM_PER_TPTC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8890]
-set CM_PER_DLL_AGING_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8898]
-set CM_PER_L4HS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a0]
-set CM_PER_L4FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a8]
-set CM_PER_L3S_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8a00]
-set CM_PER_GPMC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a20]
-set CM_PER_IEEE5000_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a28]
-set CM_PER_MCASP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a38]
-set CM_PER_MCASP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a40]
-set CM_PER_MMC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a48]
-set CM_PER_QSPI_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a58]
-set CM_PER_USB_OTG_SS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a60]
-set CM_PER_USB_OTG_SS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a68]
-set CM_PER_ICSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8b00]
-set CM_PER_ICSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8b20]
-set CM_PER_L4LS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8c00]
-set CM_PER_L4LS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c20]
-set CM_PER_DCAN0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c28]
-set CM_PER_DCAN1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c30]
-set CM_PER_EPWMSS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c38]
-set CM_PER_EPWMSS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c40]
-set CM_PER_EPWMSS2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c48]
-set CM_PER_EPWMSS3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c50]
-set CM_PER_EPWMSS4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c58]
-set CM_PER_EPWMSS5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c60]
-set CM_PER_ELM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c68]
-set CM_PER_GPIO1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c78]
-set CM_PER_GPIO2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c80]
-set CM_PER_GPIO3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c88]
-set CM_PER_GPIO4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c90]
-set CM_PER_GPIO5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c98]
-set CM_PER_HDQ1W_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca0]
-set CM_PER_I2C1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca8]
-set CM_PER_I2C2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb0]
-set CM_PER_MAILBOX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb8]
-set CM_PER_MMC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc0]
-set CM_PER_MMC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc8]
-set CM_PER_PKA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cd0]
-set CM_PER_RNG_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce0]
-set CM_PER_SPARE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce8]
-set CM_PER_SPARE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cf0]
-set CM_PER_SPI0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d00]
-set CM_PER_SPI1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d08]
-set CM_PER_SPI2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d10]
-set CM_PER_SPI3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d18]
-set CM_PER_SPI4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d20]
-set CM_PER_SPINLOCK_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d28]
-set CM_PER_TIMER2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d30]
-set CM_PER_TIMER3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d38]
-set CM_PER_TIMER4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d40]
-set CM_PER_TIMER5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d48]
-set CM_PER_TIMER6_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d50]
-set CM_PER_TIMER7_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d58]
-set CM_PER_TIMER8_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d60]
-set CM_PER_TIMER9_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d68]
-set CM_PER_TIMER10_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d70]
-set CM_PER_TIMER11_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d78]
-set CM_PER_UART1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d80]
-set CM_PER_UART2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d88]
-set CM_PER_UART3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d90]
-set CM_PER_UART4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d98]
-set CM_PER_UART5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8da0]
-set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8db8]
-set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8dc0]
-set CM_PER_EMIF_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8f00]
-set CM_PER_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f20]
-set CM_PER_DLL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f28]
-set CM_PER_EMIF_FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f30]
-set CM_PER_OTFA_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f38]
-set CM_PER_DSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9200]
-set CM_PER_DSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9220]
-set CM_PER_CPSW_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9300]
-set CM_PER_CPGMAC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9320]
-set CM_PER_OCPWP_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9400]
-set CM_PER_OCPWP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9420]
+set REVISION_PRM [expr {$PRCM_BASE_ADDR + 0x0000}]
+set PRM_IRQSTATUS_MPU [expr {$PRCM_BASE_ADDR + 0x0004}]
+set PRM_IRQENABLE_MPU [expr {$PRCM_BASE_ADDR + 0x0008}]
+set PRM_IRQSTATUS_M3 [expr {$PRCM_BASE_ADDR + 0x000c}]
+set PRM_IRQENABLE_M3 [expr {$PRCM_BASE_ADDR + 0x0010}]
+set PM_MPU_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0300}]
+set PM_MPU_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0304}]
+set RM_MPU_RSTST [expr {$PRCM_BASE_ADDR + 0x0314}]
+set RM_MPU_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0324}]
+set PM_GFX_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0400}]
+set PM_GFX_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0404}]
+set RM_GFX_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x0410}]
+set RM_GFX_RSTST [expr {$PRCM_BASE_ADDR + 0x0414}]
+set RM_GFX_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0424}]
+set RM_RTC_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0524}]
+set RM_WKUP_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x2010}]
+set RM_WKUP_RSTST [expr {$PRCM_BASE_ADDR + 0x2014}]
+set CM_L3_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2800}]
+set CM_WKUP_DEBUGSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2820}]
+set CM_L3S_TSC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2900}]
+set CM_WKUP_ADC_TSC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2920}]
+set CM_L4_WKUP_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2a00}]
+set CM_WKUP_L4WKUP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a20}]
+set CM_WKUP_WKUP_M3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a28}]
+set CM_WKUP_SYNCTIMER_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a30}]
+set CM_WKUP_CLKDIV32K_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a38}]
+set CM_WKUP_USBPHY0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a40}]
+set CM_WKUP_USBPHY1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a48}]
+set CM_WKUP_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2b00}]
+set CM_WKUP_TIMER0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b20}]
+set CM_WKUP_TIMER1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b28}]
+set CM_WKUP_WDT0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b30}]
+set CM_WKUP_WDT1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b38}]
+set CM_WKUP_I2C0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b40}]
+set CM_WKUP_UART0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b48}]
+set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b50}]
+set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b58}]
+set CM_WKUP_CONTROL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b60}]
+set CM_WKUP_GPIO0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b68}]
+set CM_CLKMODE_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d20}]
+set CM_IDLEST_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d24}]
+set CM_CLKSEL_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d2c}]
+set CM_DIV_M4_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d38}]
+set CM_DIV_M5_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d3c}]
+set CM_DIV_M6_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d40}]
+set CM_SSC_DELTAMSTEP_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d48}]
+set CM_SSC_MODFREQDIV_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d4c}]
+set CM_CLKMODE_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d60}]
+set CM_IDLEST_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d64}]
+set CM_CLKSEL_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d6c}]
+set CM_DIV_M2_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d70}]
+set CM_SSC_DELTAMSTEP_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d88}]
+set CM_SSC_MODFREQDIV_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d8c}]
+set CM_CLKMODE_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da0}]
+set CM_IDLEST_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da4}]
+set CM_CLKSEL_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dac}]
+set CM_DIV_M2_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db0}]
+set CM_DIV_M4_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db8}]
+set CM_SSC_DELTAMSTEP_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dc8}]
+set CM_SSC_MODFREQDIV_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dcc}]
+set CM_CLKMODE_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de0}]
+set CM_IDLEST_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de4}]
+set CM_CLKSEL_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2dec}]
+set CM_DIV_M2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2df0}]
+set CM_CLKSEL2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e04}]
+set CM_SSC_DELTAMSTEP_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e08}]
+set CM_SSC_MODFREQDIV_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e0c}]
+set CM_CLKDCOLDO_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e14}]
+set CM_CLKMODE_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e20}]
+set CM_IDLEST_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e24}]
+set CM_CLKSEL_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e2c}]
+set CM_DIV_M2_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e30}]
+set CM_SSC_DELTAMSTEP_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e48}]
+set CM_SSC_MODFREQDIV_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e4c}]
+set CM_CLKMODE_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e60}]
+set CM_IDLEST_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e64}]
+set CM_CLKSEL_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e6c}]
+set CM_DIV_M2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e70}]
+set CM_CLKSEL2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e84}]
+set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e88}]
+set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e8c}]
+set CM_SHADOW_FREQ_CONFIG1 [expr {$PRCM_BASE_ADDR + 0x2fa0}]
+set CM_SHADOW_FREQ_CONFIG2 [expr {$PRCM_BASE_ADDR + 0x2fa4}]
+set CM_CLKOUT1_CTRL [expr {$PRCM_BASE_ADDR + 0x4100}]
+set CM_DLL_CTRL [expr {$PRCM_BASE_ADDR + 0x4104}]
+set CM_CLKOUT2_CTRL [expr {$PRCM_BASE_ADDR + 0x4108}]
+set CLKSEL_TIMER1MS_CLK [expr {$PRCM_BASE_ADDR + 0x4200}]
+set CLKSEL_TIMER2_CLK [expr {$PRCM_BASE_ADDR + 0x4204}]
+set CLKSEL_TIMER3_CLK [expr {$PRCM_BASE_ADDR + 0x4208}]
+set CLKSEL_TIMER4_CLK [expr {$PRCM_BASE_ADDR + 0x420c}]
+set CLKSEL_TIMER5_CLK [expr {$PRCM_BASE_ADDR + 0x4210}]
+set CLKSEL_TIMER6_CLK [expr {$PRCM_BASE_ADDR + 0x4214}]
+set CLKSEL_TIMER7_CLK [expr {$PRCM_BASE_ADDR + 0x4218}]
+set CLKSEL_TIMER8_CLK [expr {$PRCM_BASE_ADDR + 0x421c}]
+set CLKSEL_TIMER9_CLK [expr {$PRCM_BASE_ADDR + 0x4220}]
+set CLKSEL_TIMER10_CLK [expr {$PRCM_BASE_ADDR + 0x4224}]
+set CLKSEL_TIMER11_CLK [expr {$PRCM_BASE_ADDR + 0x4228}]
+set CLKSEL_WDT1_CLK [expr {$PRCM_BASE_ADDR + 0x422c}]
+set CLKSEL_SYNCTIMER_CLK [expr {$PRCM_BASE_ADDR + 0x4230}]
+set CLKSEL_MAC_CLK [expr {$PRCM_BASE_ADDR + 0x4234}]
+set CLKSEL_CPTS_RFT_CLK [expr {$PRCM_BASE_ADDR + 0x4238}]
+set CLKSEL_GFX_FCLK [expr {$PRCM_BASE_ADDR + 0x423c}]
+set CLKSEL_GPIO0_DBCLK [expr {$PRCM_BASE_ADDR + 0x4240}]
+set CLKSEL_LCDC_PIXEL_CLK [expr {$PRCM_BASE_ADDR + 0x4244}]
+set CLKSEL_ICSS_OCP_CLK [expr {$PRCM_BASE_ADDR + 0x4248}]
+set CLKSEL_DLL_AGING_CLK [expr {$PRCM_BASE_ADDR + 0x4250}]
+set CLKSEL_USBPHY32KHZ_GCLK [expr {$PRCM_BASE_ADDR + 0x4260}]
+set CM_MPU_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8300}]
+set CM_MPU_MPU_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8320}]
+set CM_GFX_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8400}]
+set CM_GFX_GFX_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8420}]
+set CM_RTC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8500}]
+set CM_RTC_RTC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8520}]
+set CM_PER_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8800}]
+set CM_PER_L3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8820}]
+set CM_PER_AES0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8828}]
+set CM_PER_DES_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8830}]
+set CM_PER_CRYPTODMA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8838}]
+set CM_PER_L3_INSTR_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8840}]
+set CM_PER_MSTR_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8848}]
+set CM_PER_OCMCRAM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8850}]
+set CM_PER_SHA0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8858}]
+set CM_PER_SLV_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8860}]
+set CM_PER_VPFE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8868}]
+set CM_PER_VPFE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8870}]
+set CM_PER_TPCC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8878}]
+set CM_PER_TPTC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8880}]
+set CM_PER_TPTC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8888}]
+set CM_PER_TPTC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8890}]
+set CM_PER_DLL_AGING_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8898}]
+set CM_PER_L4HS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a0}]
+set CM_PER_L4FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a8}]
+set CM_PER_L3S_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8a00}]
+set CM_PER_GPMC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a20}]
+set CM_PER_IEEE5000_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a28}]
+set CM_PER_MCASP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a38}]
+set CM_PER_MCASP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a40}]
+set CM_PER_MMC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a48}]
+set CM_PER_QSPI_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a58}]
+set CM_PER_USB_OTG_SS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a60}]
+set CM_PER_USB_OTG_SS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a68}]
+set CM_PER_ICSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8b00}]
+set CM_PER_ICSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8b20}]
+set CM_PER_L4LS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8c00}]
+set CM_PER_L4LS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c20}]
+set CM_PER_DCAN0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c28}]
+set CM_PER_DCAN1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c30}]
+set CM_PER_EPWMSS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c38}]
+set CM_PER_EPWMSS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c40}]
+set CM_PER_EPWMSS2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c48}]
+set CM_PER_EPWMSS3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c50}]
+set CM_PER_EPWMSS4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c58}]
+set CM_PER_EPWMSS5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c60}]
+set CM_PER_ELM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c68}]
+set CM_PER_GPIO1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c78}]
+set CM_PER_GPIO2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c80}]
+set CM_PER_GPIO3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c88}]
+set CM_PER_GPIO4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c90}]
+set CM_PER_GPIO5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c98}]
+set CM_PER_HDQ1W_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca0}]
+set CM_PER_I2C1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca8}]
+set CM_PER_I2C2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb0}]
+set CM_PER_MAILBOX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb8}]
+set CM_PER_MMC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc0}]
+set CM_PER_MMC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc8}]
+set CM_PER_PKA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cd0}]
+set CM_PER_RNG_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce0}]
+set CM_PER_SPARE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce8}]
+set CM_PER_SPARE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cf0}]
+set CM_PER_SPI0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d00}]
+set CM_PER_SPI1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d08}]
+set CM_PER_SPI2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d10}]
+set CM_PER_SPI3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d18}]
+set CM_PER_SPI4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d20}]
+set CM_PER_SPINLOCK_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d28}]
+set CM_PER_TIMER2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d30}]
+set CM_PER_TIMER3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d38}]
+set CM_PER_TIMER4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d40}]
+set CM_PER_TIMER5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d48}]
+set CM_PER_TIMER6_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d50}]
+set CM_PER_TIMER7_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d58}]
+set CM_PER_TIMER8_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d60}]
+set CM_PER_TIMER9_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d68}]
+set CM_PER_TIMER10_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d70}]
+set CM_PER_TIMER11_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d78}]
+set CM_PER_UART1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d80}]
+set CM_PER_UART2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d88}]
+set CM_PER_UART3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d90}]
+set CM_PER_UART4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d98}]
+set CM_PER_UART5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8da0}]
+set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8db8}]
+set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8dc0}]
+set CM_PER_EMIF_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8f00}]
+set CM_PER_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f20}]
+set CM_PER_DLL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f28}]
+set CM_PER_EMIF_FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f30}]
+set CM_PER_OTFA_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f38}]
+set CM_PER_DSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9200}]
+set CM_PER_DSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9220}]
+set CM_PER_CPSW_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9300}]
+set CM_PER_CPGMAC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9320}]
+set CM_PER_OCPWP_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9400}]
+set CM_PER_OCPWP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9420}]