- mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
- mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
- mww 0xb8000010 0x1 ;# Forces an MRS update cycl
- mww 0xb800000c 0x2 ;# Extended mode register value.
- ;# default 0x2 - Reset to weak driver, DLL on
- mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
- mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
- mww 0xb8000008 0x33 ;# mode reg: remove some bit?
- mww 0xb8000010 0x1 ;# Forces an MRS update cycl
- mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
- mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
- ;# DQ[7:0], DQS_0
- mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
- ;# DQ[15:8], DQS_1.
- mww 0xb8000018 0xff ;# DDR read and capture bit mask.
- ;# Each bit represents a cycle of valid data.
-}