- # set ip control
- irscan $jrc 2 -endstate IRPAUSE
- drscan $jrc 32 [expr 0xa0002108 + ($port << 24)] -endstate DRPAUSE
-
- # for icepick_D
- irscan $jrc 2 -endstate IRPAUSE
- drscan $jrc 32 0xe0002008 -endstate DRPAUSE
-
- irscan $jrc 0x3F -endstate RUN/IDLE
- runtest 10
-}
-
-#
-# M3 DAP
-#
-if { [info exists M3_DAP_TAPID] } {
- set _M3_DAP_TAPID $M3_DAP_TAPID
-} else {
- set _M3_DAP_TAPID 0x4b6b902f
-}
-jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11"
-
-#
-# Main DAP
-#
-if { [info exists DAP_TAPID ] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x4b6b902f
-}
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12"
-
-#
-# ICEpick-D (JTAG route controller)
-#
-if { [info exists JRC_TAPID ] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b94402f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
-# some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
-#
-# Cortex A8 target
-#
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
-
-# SRAM: 64K at 0x4030.0000; use the first 16K
-$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
-
-$_TARGETNAME configure -event reset-assert "am335x_dbginit $_TARGETNAME"
-$_TARGETNAME configure -event reset-assert-post "am335x_dbginit $_TARGETNAME"
-
-$_TARGETNAME configure -event gdb-attach {
- global _TARGETNAME
- am335x_dbginit $_TARGETNAME
- echo "Halting target"
- halt
-}
-
-# Run this to enable invasive debugging. This is run automatically in the
-# reset sequence.
-proc am335x_dbginit {target} {
- # General Cortex A8 debug initialisation
- cortex_a8 dbginit
-}