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tcl/board: add SPDX tag
[fw/openocd]
/
tcl
/
board
/
icnova_imx53_sodimm.cfg
diff --git
a/tcl/board/icnova_imx53_sodimm.cfg
b/tcl/board/icnova_imx53_sodimm.cfg
index 0a161f6cd581c27939eb674660089f18823ec2b4..c4e8bdec0b8fe71c12186eb9407215341239f81b 100644
(file)
--- a/
tcl/board/icnova_imx53_sodimm.cfg
+++ b/
tcl/board/icnova_imx53_sodimm.cfg
@@
-1,3
+1,5
@@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
#################################################################################################
# Author: Benjamin Tietz <benjamin.tietz@in-circuit.de> ;#
# based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> ;#
#################################################################################################
# Author: Benjamin Tietz <benjamin.tietz@in-circuit.de> ;#
# based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> ;#
@@
-69,7
+71,7
@@
proc init_l2cc { } {
set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1
set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1
- arm mcr 15 0 1 0 1 [expr
$tR & ~(1<<2)
]
+ arm mcr 15 0 1 0 1 [expr
{$tR & ~(1 << 2)}
]
; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */
; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */
@@
-139,7
+141,7
@@
proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2
- mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr
[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000
]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr
{[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}
]
; # make sure change is effective
while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
; # make sure change is effective
while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
@@
-157,7
+159,7
@@
proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6
- mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr
[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a
]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr
{[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}
]
; # Restore the default values in the Gate registers
mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
; # Restore the default values in the Gate registers
mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
@@
-243,7
+245,7
@@
proc setup_pll { PLL_ADDR CLK } {
mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
- while {[expr
[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1
] == 0} { sleep 1 }
+ while {[expr
{[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}
] == 0} { sleep 1 }
}
}