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tcl/target/stm32(f7/h7)x: do not assume presence of the reset
[fw/openocd]
/
tcl
/
board
/
eir.cfg
diff --git
a/tcl/board/eir.cfg
b/tcl/board/eir.cfg
index 3754a4227de30d625d389c07deff910a51ace014..67758b81e1880483b38492ea9b90baa221652ecb 100644
(file)
--- a/
tcl/board/eir.cfg
+++ b/
tcl/board/eir.cfg
@@
-1,7
+1,7
@@
# Elector Internet Radio board
# http://www.ethernut.de/en/hardware/eir/index.html
# Elector Internet Radio board
# http://www.ethernut.de/en/hardware/eir/index.html
-source [find target/sam7se512.cfg]
+source [find target/
at91
sam7se512.cfg]
$_TARGETNAME configure -event reset-init {
# WDT_MR, disable watchdog
$_TARGETNAME configure -event reset-init {
# WDT_MR, disable watchdog
@@
-30,60
+30,60
@@
$_TARGETNAME configure -event reset-init {
#
# Enable SDRAM control at PIO A.
#
# Enable SDRAM control at PIO A.
- mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
- mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
+ mww 0xfffff474 0x3f800000
;
# PIO_BSR_OFF
+ mww 0xfffff404 0x3f800000
;
# PIO_PDR_OFF
# Enable address bus (A0, A2-A11, A13-A17) at PIO B
# Enable address bus (A0, A2-A11, A13-A17) at PIO B
- mww 0xfffff674 0x0003effd # PIO_BSR_OFF
- mww 0xfffff604 0x0003effd # PIO_PDR_OFF
+ mww 0xfffff674 0x0003effd
;
# PIO_BSR_OFF
+ mww 0xfffff604 0x0003effd
;
# PIO_PDR_OFF
# Enable 16 bit data bus at PIO C
# Enable 16 bit data bus at PIO C
- mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
- mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
+ mww 0xfffff870 0x0000ffff
;
# PIO_ASR_OFF
+ mww 0xfffff804 0x0000ffff
;
# PIO_PDR_OFF
# Enable SDRAM chip select
# Enable SDRAM chip select
- mww 0xffffff80 0x00000002 # EBI_CSA_OFF
+ mww 0xffffff80 0x00000002
;
# EBI_CSA_OFF
# Set SDRAM characteristics in configuration register.
# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
# Set SDRAM characteristics in configuration register.
# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
- mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
+ mww 0xffffffb8 0x2192215a
;
# SDRAMC_CR_OFF
sleep 10
# Issue 16 bit SDRAM command: NOP
sleep 10
# Issue 16 bit SDRAM command: NOP
- mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000011
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
# Issue 16 bit SDRAM command: Precharge all
mww 0x20000000 0x00000000
# Issue 16 bit SDRAM command: Precharge all
- mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000012
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
# Issue 8 auto-refresh cycles
mww 0x20000000 0x00000000
# Issue 8 auto-refresh cycles
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
# Issue 16 bit SDRAM command: Set mode register
mww 0x20000000 0x00000000
# Issue 16 bit SDRAM command: Set mode register
- mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000013
;
# SDRAMC_MR_OFF
mww 0x20000014 0xcafedede
# Set refresh rate count ???
mww 0x20000014 0xcafedede
# Set refresh rate count ???
- mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
+ mww 0xffffffb4 0x00000013
;
# SDRAMC_TR_OFF
# Issue 16 bit SDRAM command: Normal mode
# Issue 16 bit SDRAM command: Normal mode
- mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000010
;
# SDRAMC_MR_OFF
mww 0x20000000 0x00000180
#
mww 0x20000000 0x00000180
#
@@
-91,4
+91,3
@@
$_TARGETNAME configure -event reset-init {
#
mww 0xfffffd08 0xa5000001
}
#
mww 0xfffffd08 0xa5000001
}
-