+ # VTPIOCR impedance calibration
+ set addr [dict get $dm355 sysbase]
+ set addr [expr {$addr + 0x70}]
+
+ # clear CLR, LOCK, PWRDN; wait a clock; set CLR
+ mmw $addr 0 0x20c0
+ mmw $addr 0x2000 0
+
+ # wait for READY
+ while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
+
+ # set IO_READY; then LOCK and PWRSAVE; then PWRDN
+ mmw $addr 0x4000 0
+ mmw $addr 0x0180 0
+ mmw $addr 0x0040 0
+
+ # NOTE: this DDR2 initialization sequence borrows from
+ # both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
+
+ # reset (then re-enable) DDR controller
+ psc_reset 13
+ psc_go
+ psc_enable 13
+ psc_go
+
+ # now set it up for Micron MT47H64M16HR-37E @ 171 MHz
+
+ set addr [dict get $dm355 ddr_emif]
+
+ # DDRPHYCR1
+ mww [expr {$addr + 0xe4}] 0x50006404
+
+ # PBBPR -- burst priority
+ mww [expr {$addr + 0x20}] 0xfe
+
+ # SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
+ mmw [expr {$addr + 0x08}] 0x00800000 0
+ mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
+
+ # SDTIMR0, SDTIMR1
+ mww [expr {$addr + 0x10}] 0x2a923249
+ mww [expr {$addr + 0x14}] 0x4c17c763
+
+ # SDCR -- relock SDTIM*
+ mmw [expr {$addr + 0x08}] 0 0x00008000
+
+ # SDRCR -- refresh rate (171 MHz * 7.8usec)
+ mww [expr {$addr + 0x0c}] 1336