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cfg: Beaglebone/AM335x refactor
[fw/openocd]
/
tcl
/
board
/
csb732.cfg
diff --git
a/tcl/board/csb732.cfg
b/tcl/board/csb732.cfg
index 8bf77cb3b348c115a07182dd75a5494dabf42378..4d6f0e489e6fe0e44c4d95e7ac82f114151ec055 100644
(file)
--- a/
tcl/board/csb732.cfg
+++ b/
tcl/board/csb732.cfg
@@
-3,7
+3,7
@@
source [find target/imx35.cfg]
# Determined by trial and error
reset_config trst_and_srst combined
# Determined by trial and error
reset_config trst_and_srst combined
-
jtag
_nsrst_delay 200
+
adapter
_nsrst_delay 200
jtag_ntrst_delay 200
$_TARGETNAME configure -event gdb-attach { reset init }
jtag_ntrst_delay 200
$_TARGETNAME configure -event gdb-attach { reset init }
@@
-11,7
+11,7
@@
$_TARGETNAME configure -event reset-init { csb732_init }
# Bare-bones initialization of core clocks and SDRAM
proc csb732_init { } {
# Bare-bones initialization of core clocks and SDRAM
proc csb732_init { } {
-
+
# Disable fast writing only for init
memwrite burst disable
# Disable fast writing only for init
memwrite burst disable
@@
-19,27
+19,27
@@
proc csb732_init { } {
# We assume the interpreter latency is enough.
# Allow access to all coprocessors
# We assume the interpreter latency is enough.
# Allow access to all coprocessors
- arm
11 mcr imx35.cpu
15 0 15 1 0 0x2001
+ arm
mcr
15 0 15 1 0 0x2001
# Disable MMU, caches, write buffer
# Disable MMU, caches, write buffer
- arm
11 mcr imx35.cpu
15 0 1 0 0 0x78
+ arm
mcr
15 0 1 0 0 0x78
# Grant manager access to all domains
# Grant manager access to all domains
- arm
11 mcr imx35.cpu
15 0 3 0 0 0xFFFFFFFF
+ arm
mcr
15 0 3 0 0 0xFFFFFFFF
# Set ARM clock to 532 MHz, AHB to 133 MHz
mww 0x53F80004 0x1000
# Set ARM clock to 532 MHz, AHB to 133 MHz
mww 0x53F80004 0x1000
-
+
# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
mww 0x53F8001C 0xB2C01
# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
mww 0x53F8001C 0xB2C01
-
+
set ESDMISC 0xB8001010
set ESDCFG0 0xB8001004
set ESDCTL0 0xB8001000
# Enable DDR
mww $ESDMISC 0x4
set ESDMISC 0xB8001010
set ESDCFG0 0xB8001004
set ESDCTL0 0xB8001000
# Enable DDR
mww $ESDMISC 0x4
-
+
# Timing
mww $ESDCFG0 0x007fff3f
# Timing
mww $ESDCFG0 0x007fff3f
@@
-51,7
+51,7
@@
proc csb732_init { } {
# Enable CS) auto-refresh
mww $ESDCTL0 0xA2120080
# Enable CS) auto-refresh
mww $ESDCTL0 0xA2120080
-
+
# Refresh twice (dummy writes)
mww 0x80000000 0
mww 0x80000000 0
# Refresh twice (dummy writes)
mww 0x80000000 0
mww 0x80000000 0
@@
-59,7
+59,7
@@
proc csb732_init { } {
# Enable CS0 load mode register
mww $ESDCTL0 0xB2120080
# Enable CS0 load mode register
mww $ESDCTL0 0xB2120080
- # Dummy writes
+ # Dummy writes
mwb 0x80000033 0x01
mwb 0x81000000 0x01
mwb 0x80000033 0x01
mwb 0x81000000 0x01