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cfg: beaglebone cleanup
[fw/openocd]
/
tcl
/
board
/
csb337.cfg
diff --git
a/tcl/board/csb337.cfg
b/tcl/board/csb337.cfg
index dd8bfa2de970ed8da7899bdf049ccbeaa65fd03b..5e225f5f549de04f21d3dabe413cbe130d36ad26 100644
(file)
--- a/
tcl/board/csb337.cfg
+++ b/
tcl/board/csb337.cfg
@@
-4,7
+4,8
@@
source [find target/at91rm9200.cfg]
# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
source [find target/at91rm9200.cfg]
# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
-flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
# ETM9 trace port connector present on this board, 16 data pins.
if { [info exists ETM_DRIVER] } {
# ETM9 trace port connector present on this board, 16 data pins.
if { [info exists ETM_DRIVER] } {
@@
-18,7
+19,7
@@
if { [info exists ETM_DRIVER] } {
proc csb337_clk_init { } {
# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
proc csb337_clk_init { } {
# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
-
jtag
_khz 8
+
adapter
_khz 8
# CKGR_MOR: start main oscillator (3.6864 MHz)
mww 0xfffffc20 0xff01
# CKGR_MOR: start main oscillator (3.6864 MHz)
mww 0xfffffc20 0xff01
@@
-36,7
+37,7
@@
proc csb337_clk_init { } {
sleep 20
# CPU is in Normal Mode ... allows faster JTAG clock speed
sleep 20
# CPU is in Normal Mode ... allows faster JTAG clock speed
-
jtag
_khz 40000
+
adapter
_khz 40000
}
proc csb337_nor_init { } {
}
proc csb337_nor_init { } {
@@
-113,4
+114,4
@@
proc csb337_reset_init { } {
$_TARGETNAME configure -event reset-init {csb337_reset_init}
$_TARGETNAME configure -event reset-init {csb337_reset_init}
-# vim:syntax tcl
+arm7_9 fast_memory_access enable