+replace {
+ rlca
+ ld a,#0x00
+ rla
+} by {
+ rlca
+ and a,#0x01
+}
+replace {
+ ld %3,a
+ ld l,%1
+ ld h,%2
+ ld l,(hl)
+ ld a,%3
+} by {
+ ld %3,a
+ ld l,%1
+ ld h,%2
+ ld l,(hl)
+} if notVolatile %3
+
+;
+;--------------------------
+;
+replace restart {
+ pop %1
+ push %1
+ ld %1,%2
+} by {
+ ; z80 removed redundant pop/push
+ ld %1,%2
+}
+
+replace restart {
+ ld l,a
+ ld c,%1
+ ld a,l
+} by {
+ ld l,a
+ ld c,%1
+}
+
+replace restart {
+ ld c,l
+ ld a,c
+ and a,#%1
+ ld c,a
+ or a,a
+} by {
+ ; z80 stream lining 'and' logic
+ ld a,#%1
+ and a,l
+ ld c,a
+}
+
+replace restart {
+ ld a,c
+ and a,#%1
+ ld c,a
+ or a,a
+} by {
+ ; z80 stream lining 'and' logic
+ ld a,#%1
+ and a,c
+ ld c,a
+}
+
+replace restart {
+ ld a,c
+ or a,#%1
+ ld c,a
+} by {
+ ; z80 stream lining 'or' logic
+ ld a,#%1
+ or a,c
+ ld c,a
+}
+
+
+replace {
+%1:
+ in0 a,(%2)
+ and a,#%3
+ jp z,%4
+%5:
+ jp %6
+%4:
+ call %7
+ jp %1
+%6:
+ ret
+} by {
+%1:
+ in0 a,(%2)
+ and a,#%3
+ jp nz,%5
+%4:
+ call %7
+ jp %1
+%5:
+%6:
+ ret
+}
+
+