+
+ int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address,
+ uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
+
+ int (*sample_memory)(struct target *target,
+ struct riscv_sample_buf *buf,
+ riscv_sample_config_t *config,
+ int64_t until_ms);
+
+ int (*read_memory)(struct target *target, target_addr_t address,
+ uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
+
+ /* How many harts are attached to the DM that this target is attached to? */
+ int (*hart_count)(struct target *target);
+ unsigned (*data_bits)(struct target *target);
+
+ COMMAND_HELPER((*print_info), struct target *target);
+
+ /* Storage for vector register types. */
+ struct reg_data_type_vector vector_uint8;
+ struct reg_data_type_vector vector_uint16;
+ struct reg_data_type_vector vector_uint32;
+ struct reg_data_type_vector vector_uint64;
+ struct reg_data_type_vector vector_uint128;
+ struct reg_data_type type_uint8_vector;
+ struct reg_data_type type_uint16_vector;
+ struct reg_data_type type_uint32_vector;
+ struct reg_data_type type_uint64_vector;
+ struct reg_data_type type_uint128_vector;
+ struct reg_data_type_union_field vector_fields[5];
+ struct reg_data_type_union vector_union;
+ struct reg_data_type type_vector;
+
+ /* Set when trigger registers are changed by the user. This indicates we eed
+ * to beware that we may hit a trigger that we didn't realize had been set. */
+ bool manual_hwbp_set;
+
+ /* Memory access methods to use, ordered by priority, highest to lowest. */
+ int mem_access_methods[RISCV_NUM_MEM_ACCESS_METHODS];
+
+ /* Different memory regions may need different methods but single configuration is applied
+ * for all. Following flags are used to warn only once about failing memory access method. */
+ bool mem_access_progbuf_warn;
+ bool mem_access_sysbus_warn;
+ bool mem_access_abstract_warn;
+
+ /* In addition to the ones in the standard spec, we'll also expose additional
+ * CSRs in this list. */
+ struct list_head expose_csr;
+ /* Same, but for custom registers.
+ * Custom registers are for non-standard extensions and use abstract register numbers
+ * from range 0xc000 ... 0xffff. */
+ struct list_head expose_custom;
+
+ riscv_sample_config_t sample_config;
+ struct riscv_sample_buf sample_buf;