+
+COMMAND_HANDLER(mips_m4k_handle_cp0_command)
+{
+ int retval;
+ struct target *target = get_current_target(CMD_CTX);
+ struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+ struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
+
+ retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target->state != TARGET_HALTED) {
+ command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_OK;
+ }
+
+ /* two or more argument, access a single register/select (write if third argument is given) */
+ if (CMD_ARGC < 2)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ else {
+ uint32_t cp0_reg, cp0_sel;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
+
+ if (CMD_ARGC == 2) {
+ uint32_t value;
+
+ retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
+ if (retval != ERROR_OK) {
+ command_print(CMD_CTX,
+ "couldn't access reg %" PRIi32,
+ cp0_reg);
+ return ERROR_OK;
+ }
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
+
+ command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+ cp0_reg, cp0_sel, value);
+ } else if (CMD_ARGC == 3) {
+ uint32_t value;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
+ retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
+ if (retval != ERROR_OK) {
+ command_print(CMD_CTX,
+ "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
+ cp0_reg, cp0_sel);
+ return ERROR_OK;
+ }
+ command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+ cp0_reg, cp0_sel, value);
+ }
+ }
+
+ return ERROR_OK;
+}
+
+static const struct command_registration mips_m4k_exec_command_handlers[] = {
+ {
+ .name = "cp0",
+ .handler = mips_m4k_handle_cp0_command,
+ .mode = COMMAND_EXEC,
+ .usage = "regnum [value]",
+ .help = "display/modify cp0 register",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+const struct command_registration mips_m4k_command_handlers[] = {
+ {
+ .chain = mips32_command_handlers,
+ },
+ {
+ .name = "mips_m4k",
+ .mode = COMMAND_ANY,
+ .help = "mips_m4k command group",
+ .usage = "",
+ .chain = mips_m4k_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct target_type mips_m4k_target = {
+ .name = "mips_m4k",
+
+ .poll = mips_m4k_poll,
+ .arch_state = mips32_arch_state,
+
+ .target_request_data = NULL,
+
+ .halt = mips_m4k_halt,
+ .resume = mips_m4k_resume,
+ .step = mips_m4k_step,
+
+ .assert_reset = mips_m4k_assert_reset,
+ .deassert_reset = mips_m4k_deassert_reset,
+ .soft_reset_halt = mips_m4k_soft_reset_halt,
+
+ .get_gdb_reg_list = mips32_get_gdb_reg_list,
+
+ .read_memory = mips_m4k_read_memory,
+ .write_memory = mips_m4k_write_memory,
+ .bulk_write_memory = mips_m4k_bulk_write_memory,
+ .checksum_memory = mips32_checksum_memory,
+ .blank_check_memory = mips32_blank_check_memory,
+
+ .run_algorithm = mips32_run_algorithm,
+
+ .add_breakpoint = mips_m4k_add_breakpoint,
+ .remove_breakpoint = mips_m4k_remove_breakpoint,
+ .add_watchpoint = mips_m4k_add_watchpoint,
+ .remove_watchpoint = mips_m4k_remove_watchpoint,
+
+ .commands = mips_m4k_command_handlers,
+ .target_create = mips_m4k_target_create,
+ .init_target = mips_m4k_init_target,
+ .examine = mips_m4k_examine,
+};