-/* implementaion register bits */
-#define EJTAG_IMP_R3K (1 << 28)
-#define EJTAG_IMP_DINT (1 << 24)
-#define EJTAG_IMP_NODMA (1 << 14)
+/* implementation MIPS register bits.
+ * Bits marked with V20 or v2.0 mean that, this registers supported only
+ * by EJTAG v2.0. Bits marked with Lexra or BMIPS are different from the
+ * official EJATG.
+ * NOTE: Lexra or BMIPS use EJTAG v2.0 */
+
+#define EJTAG_IMP_HAS(x) (ejtag_info->impcode & (x))
+/* v2.0(Lexra) 29 - 1’b1 - Lexra Internal Trace Buffer implemented. This bit
+ * overlaps with version bit of MIPS EJTAG specification. */
+#define EJTAG_V26_IMP_R3K (1 << 28)
+/* v2.0 - 24:25 - 2’b00- No profiling support */
+#define EJTAG_V26_IMP_DINT (1 << 24)
+#define EJTAG_V20_IMP_SDBBP (1 << 23) /* 1’b1 - sdbbp is Special2 Opcode */
+#define EJTAG_IMP_ASID8 (1 << 22)
+#define EJTAG_IMP_ASID6 (1 << 21)
+#define EJTAG_V20_IMP_COMPLEX_BREAK (1 << 20) /* Complex Breaks supported*/
+#define EJTAG_V20_IMP_EADDR_NO32BIT (1 << 19) /* EJTAG_ADDR > 32 bits wide */
+#define EJTAG_V20_IMP_DCACHE_COH (1 << 18) /* DCache does keep DMA coherent */
+#define EJTAG_V20_IMP_ICACHE_COH (1 << 17) /* DCache does keep DMA coherent */