+ return retval;
+}
+
+int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel)
+{
+ /**
+ * Do not make this code static, but regenerate it every time,
+ * as 5th element has to be changed to add parameters
+ */
+ uint32_t code[] = {
+ /* start: */
+ MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
+ MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
+ MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
+ MIPS32_SW(8, 0, 15), /* sw $8,($15) */
+ MIPS32_SW(9, 0, 15), /* sw $9,($15) */
+
+ /* 5 */ MIPS32_MFC0(8, 0, 0), /* move COP0 [cp0_reg select] to $8 */
+
+ MIPS32_LUI(9, UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */
+ MIPS32_ORI(9, 9, LOWER16(MIPS32_PRACC_PARAM_OUT)),
+ MIPS32_SW(8, 0, 9), /* sw $8,0($9) */
+
+ MIPS32_LW(9, 0, 15), /* lw $9,($15) */
+ MIPS32_LW(8, 0, 15), /* lw $8,($15) */
+ MIPS32_B(NEG16(12)), /* b start */
+ MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
+ };
+
+ /**
+ * Note that our input parametes cp0_reg and cp0_sel
+ * are numbers (not gprs) which make part of mfc0 instruction opcode.
+ *
+ * These are not fix, but can be different for each mips32_cp0_read() function call,
+ * and that is why we must insert them directly into opcode,
+ * i.e. we can not pass it on EJTAG microprogram stack (via param_in),
+ * and put them into the gprs later from MIPS32_PRACC_STACK
+ * because mfc0 do not use gpr as a parameter for the cp0_reg and select part,
+ * but plain (immediate) number.
+ *
+ * MIPS32_MTC0 is implemented via MIPS32_R_INST macro.
+ * In order to insert our parameters, we must change rd and funct fields.
+ */
+ code[5] |= (cp0_reg << 11) | cp0_sel; /* change rd and funct of MIPS32_R_INST macro */
+
+ /* TODO remove array */
+ uint32_t *param_out = val;
+ int retval;
+
+ retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 0, NULL, 1, param_out, 1);
+
+ return retval;
+}
+
+int mips32_cp0_write(struct mips_ejtag *ejtag_info,
+ uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
+{
+ uint32_t code[] = {
+ /* start: */
+ MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
+ MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
+ MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
+ MIPS32_SW(8, 0, 15), /* sw $8,($15) */
+ MIPS32_SW(9, 0, 15), /* sw $9,($15) */
+
+ MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
+ MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)),
+ MIPS32_LW(9, 0, 8), /* Load write val to $9 */
+
+ /* 8 */ MIPS32_MTC0(9, 0, 0), /* move $9 to COP0 [cp0_reg select] */
+
+ MIPS32_LW(9, 0, 15), /* lw $9,($15) */
+ MIPS32_LW(8, 0, 15), /* lw $8,($15) */
+ MIPS32_B(NEG16(12)), /* b start */
+ MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
+ };
+
+ /**
+ * Note that MIPS32_MTC0 macro is implemented via MIPS32_R_INST macro.
+ * In order to insert our parameters, we must change rd and funct fields.
+ */
+ code[8] |= (cp0_reg << 11) | cp0_sel; /* change rd and funct fields of MIPS32_R_INST macro */
+
+ /* TODO remove array */
+ uint32_t *param_in = malloc(1 * sizeof(uint32_t));
+ int retval;
+ param_in[0] = val;
+
+ retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 1, param_in, 0, NULL, 1);
+
+ free(param_in);
+
+ return retval;
+}
+
+/**
+ * \b mips32_pracc_sync_cache
+ *
+ * Synchronize Caches to Make Instruction Writes Effective
+ * (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set,
+ * Document Number: MD00086, Revision 2.00, June 9, 2003)
+ *
+ * When the instruction stream is written, the SYNCI instruction should be used
+ * in conjunction with other instructions to make the newly-written instructions effective.
+ *
+ * Explanation :
+ * A program that loads another program into memory is actually writing the D- side cache.
+ * The instructions it has loaded can't be executed until they reach the I-cache.
+ *
+ * After the instructions have been written, the loader should arrange
+ * to write back any containing D-cache line and invalidate any locations
+ * already in the I-cache.
+ *
+ * You can do that with cache instructions, but those instructions are only available in kernel mode,
+ * and a loader writing instructions for the use of its own process need not be privileged software.
+ *
+ * In the latest MIPS32/64 CPUs, MIPS provides the synci instruction,
+ * which does the whole job for a cache-line-sized chunk of the memory you just loaded:
+ * That is, it arranges a D-cache write-back and an I-cache invalidate.
+ *
+ * To employ synci at user level, you need to know the size of a cache line,
+ * and that can be obtained with a rdhwr SYNCI_Step
+ * from one of the standard “hardware registers”.
+ */
+static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info,
+ uint32_t start_addr, uint32_t end_addr)
+{
+ static const uint32_t code[] = {
+ /* start: */
+ MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
+ MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
+ MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
+ MIPS32_SW(8, 0, 15), /* sw $8,($15) */
+ MIPS32_SW(9, 0, 15), /* sw $9,($15) */
+ MIPS32_SW(10, 0, 15), /* sw $10,($15) */
+ MIPS32_SW(11, 0, 15), /* sw $11,($15) */
+
+ MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
+ MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)),
+ MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */
+ MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */
+
+ MIPS32_RDHWR(11, MIPS32_SYNCI_STEP), /* $11 = MIPS32_SYNCI_STEP */
+ MIPS32_BEQ(11, 0, 6), /* beq $11, $0, end */
+ MIPS32_NOP,
+ /* synci_loop : */
+ MIPS32_SYNCI(0, 9), /* synci 0($9) */
+ MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */
+ MIPS32_BNE(8, 0, NEG16(3)), /* bne $8, $0, synci_loop */
+ MIPS32_ADDU(9, 9, 11), /* $9 += MIPS32_SYNCI_STEP */
+ MIPS32_SYNC,
+ /* end: */
+ MIPS32_LW(11, 0, 15), /* lw $11,($15) */
+ MIPS32_LW(10, 0, 15), /* lw $10,($15) */
+ MIPS32_LW(9, 0, 15), /* lw $9,($15) */
+ MIPS32_LW(8, 0, 15), /* lw $8,($15) */
+ MIPS32_B(NEG16(24)), /* b start */
+ MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
+ };
+
+ /* TODO remove array */
+ uint32_t *param_in = malloc(2 * sizeof(uint32_t));
+ int retval;
+ param_in[0] = start_addr;
+ param_in[1] = end_addr;
+
+ retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 2, param_in, 0, NULL, 1);
+
+ free(param_in);
+
+ return retval;