+
+int mips32_checksum_memory(struct target *target, uint32_t address,
+ uint32_t count, uint32_t *checksum)
+{
+ struct working_area *crc_algorithm;
+ struct reg_param reg_params[2];
+ struct mips32_algorithm mips32_info;
+ int retval;
+ uint32_t i;
+
+ /* see contib/loaders/checksum/mips32.s for src */
+
+ static const uint32_t mips_crc_code[] = {
+ 0x248C0000, /* addiu $t4, $a0, 0 */
+ 0x24AA0000, /* addiu $t2, $a1, 0 */
+ 0x2404FFFF, /* addiu $a0, $zero, 0xffffffff */
+ 0x10000010, /* beq $zero, $zero, ncomp */
+ 0x240B0000, /* addiu $t3, $zero, 0 */
+ /* nbyte: */
+ 0x81850000, /* lb $a1, ($t4) */
+ 0x218C0001, /* addi $t4, $t4, 1 */
+ 0x00052E00, /* sll $a1, $a1, 24 */
+ 0x3C0204C1, /* lui $v0, 0x04c1 */
+ 0x00852026, /* xor $a0, $a0, $a1 */
+ 0x34471DB7, /* ori $a3, $v0, 0x1db7 */
+ 0x00003021, /* addu $a2, $zero, $zero */
+ /* loop: */
+ 0x00044040, /* sll $t0, $a0, 1 */
+ 0x24C60001, /* addiu $a2, $a2, 1 */
+ 0x28840000, /* slti $a0, $a0, 0 */
+ 0x01074826, /* xor $t1, $t0, $a3 */
+ 0x0124400B, /* movn $t0, $t1, $a0 */
+ 0x28C30008, /* slti $v1, $a2, 8 */
+ 0x1460FFF9, /* bne $v1, $zero, loop */
+ 0x01002021, /* addu $a0, $t0, $zero */
+ /* ncomp: */
+ 0x154BFFF0, /* bne $t2, $t3, nbyte */
+ 0x256B0001, /* addiu $t3, $t3, 1 */
+ 0x7000003F, /* sdbbp */
+ };
+
+ /* make sure we have a working area */
+ if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+
+ /* convert flash writing code into a buffer in target endianness */
+ for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++)
+ target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]);
+
+ mips32_info.common_magic = MIPS32_COMMON_MAGIC;
+ mips32_info.isa_mode = MIPS32_ISA_MIPS32;
+
+ init_reg_param(®_params[0], "a0", 32, PARAM_IN_OUT);
+ buf_set_u32(reg_params[0].value, 0, 32, address);
+
+ init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
+ buf_set_u32(reg_params[1].value, 0, 32, count);
+
+ int timeout = 20000 * (1 + (count / (1024 * 1024)));
+
+ retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
+ crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout,
+ &mips32_info);
+ if (retval != ERROR_OK) {
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ target_free_working_area(target, crc_algorithm);
+ return 0;
+ }
+
+ *checksum = buf_get_u32(reg_params[0].value, 0, 32);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+
+ target_free_working_area(target, crc_algorithm);
+
+ return ERROR_OK;
+}
+
+/** Checks whether a memory region is zeroed. */
+int mips32_blank_check_memory(struct target *target,
+ uint32_t address, uint32_t count, uint32_t *blank)
+{
+ struct working_area *erase_check_algorithm;
+ struct reg_param reg_params[3];
+ struct mips32_algorithm mips32_info;
+ int retval;
+ uint32_t i;
+
+ static const uint32_t erase_check_code[] = {
+ /* nbyte: */
+ 0x80880000, /* lb $t0, ($a0) */
+ 0x00C83024, /* and $a2, $a2, $t0 */
+ 0x24A5FFFF, /* addiu $a1, $a1, -1 */
+ 0x14A0FFFC, /* bne $a1, $zero, nbyte */
+ 0x24840001, /* addiu $a0, $a0, 1 */
+ 0x7000003F /* sdbbp */
+ };
+
+ /* make sure we have a working area */
+ if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+
+ /* convert flash writing code into a buffer in target endianness */
+ for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) {
+ target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t),
+ erase_check_code[i]);
+ }
+
+ mips32_info.common_magic = MIPS32_COMMON_MAGIC;
+ mips32_info.isa_mode = MIPS32_ISA_MIPS32;
+
+ init_reg_param(®_params[0], "a0", 32, PARAM_OUT);
+ buf_set_u32(reg_params[0].value, 0, 32, address);
+
+ init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
+ buf_set_u32(reg_params[1].value, 0, 32, count);
+
+ init_reg_param(®_params[2], "a2", 32, PARAM_IN_OUT);
+ buf_set_u32(reg_params[2].value, 0, 32, 0xff);
+
+ retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+ erase_check_algorithm->address,
+ erase_check_algorithm->address + (sizeof(erase_check_code)-2),
+ 10000, &mips32_info);
+ if (retval != ERROR_OK) {
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ target_free_working_area(target, erase_check_algorithm);
+ return 0;
+ }
+
+ *blank = buf_get_u32(reg_params[2].value, 0, 32);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+
+ target_free_working_area(target, erase_check_algorithm);
+
+ return ERROR_OK;
+}
+
+static int mips32_verify_pointer(struct command_context *cmd_ctx,
+ struct mips32_common *mips32)
+{
+ if (mips32->common_magic != MIPS32_COMMON_MAGIC) {
+ command_print(cmd_ctx, "target is not an MIPS32");
+ return ERROR_TARGET_INVALID;
+ }
+ return ERROR_OK;
+}
+
+/**
+ * MIPS32 targets expose command interface
+ * to manipulate CP0 registers
+ */
+COMMAND_HANDLER(mips32_handle_cp0_command)
+{
+ int retval;
+ struct target *target = get_current_target(CMD_CTX);
+ struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+
+
+ retval = mips32_verify_pointer(CMD_CTX, mips32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target->state != TARGET_HALTED) {
+ command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_OK;
+ }
+
+ /* two or more argument, access a single register/select (write if third argument is given) */
+ if (CMD_ARGC < 2)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ else {
+ uint32_t cp0_reg, cp0_sel;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
+
+ if (CMD_ARGC == 2) {
+ uint32_t value;
+
+ retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
+ if (retval != ERROR_OK) {
+ command_print(CMD_CTX,
+ "couldn't access reg %" PRIi32,
+ cp0_reg);
+ return ERROR_OK;
+ }
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
+
+ command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+ cp0_reg, cp0_sel, value);
+ } else if (CMD_ARGC == 3) {
+ uint32_t value;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
+ retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
+ if (retval != ERROR_OK) {
+ command_print(CMD_CTX,
+ "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
+ cp0_reg, cp0_sel);
+ return ERROR_OK;
+ }
+ command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+ cp0_reg, cp0_sel, value);
+ }
+ }
+
+ return ERROR_OK;
+}
+
+static const struct command_registration mips32_exec_command_handlers[] = {
+ {
+ .name = "cp0",
+ .handler = mips32_handle_cp0_command,
+ .mode = COMMAND_EXEC,
+ .usage = "regnum select [value]",
+ .help = "display/modify cp0 register",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+const struct command_registration mips32_command_handlers[] = {
+ {
+ .name = "mips32",
+ .mode = COMMAND_ANY,
+ .help = "mips32 command group",
+ .usage = "",
+ .chain = mips32_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};