uint32_t mask, uint32_t* core_regs[16])
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint32_t mask, uint32_t* core_regs[16])
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
uint32_t mask, void* buffer, int size)
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint32_t mask, void* buffer, int size)
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
/* MRS r0, cpsr */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
/* MRS r0, cpsr */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
}
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
}
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
uint32_t mask, uint32_t core_regs[16])
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
uint32_t mask, uint32_t core_regs[16])
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-static int fa526_init_arch_info_2(target_t *target,
- struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap)
+static int fa526_init_arch_info_2(struct target *target,
+ struct arm7_9_common *arm7_9, struct jtag_tap *tap)
/* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 5;
/* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 5;
- /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
- */
- fa526_init_arch_info_2(target, arm9tdmi, tap);
+ /* initialize arm7/arm9 specific info (including armv4_5) */
+ fa526_init_arch_info_2(target, arm7_9, tap);
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm920t_soft_reset_halt,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm920t_soft_reset_halt,
.read_memory = arm920t_read_memory,
.write_memory = arm920t_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.read_memory = arm920t_read_memory,
.write_memory = arm920t_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
.target_create = fa526_target_create,
.init_target = arm9tdmi_init_target,
.target_create = fa526_target_create,
.init_target = arm9tdmi_init_target,