+/**
+ * Receive a block of size 32-bit words from the DCC.
+ * We assume the target is always going to be fast enough (relative to
+ * the JTAG clock) that the debugger won't need to poll the handshake
+ * bit. The JTAG clock is usually at least six times slower than the
+ * functional clock, so the 50+ JTAG clocks needed to receive the word
+ * allow hundreds of instruction cycles (per word) in the target.
+ */
+int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
+{
+ struct scan_field fields[3];
+ uint8_t field1_out[1];
+ uint8_t field2_out[1];
+
+ jtag_set_end_state(TAP_IDLE);
+ arm_jtag_scann(jtag_info, 0x2);
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+
+ fields[0].tap = jtag_info->tap;
+ fields[0].num_bits = 32;
+ fields[0].out_value = NULL;
+ fields[0].in_value = NULL;
+
+ fields[1].tap = jtag_info->tap;
+ fields[1].num_bits = 5;
+ fields[1].out_value = field1_out;
+ buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+ fields[1].in_value = NULL;
+
+ fields[2].tap = jtag_info->tap;
+ fields[2].num_bits = 1;
+ fields[2].out_value = field2_out;
+ buf_set_u32(fields[2].out_value, 0, 1, 0);
+ fields[2].in_value = NULL;
+
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
+
+ while (size > 0)
+ {
+ /* when reading the last item, set the register address to the DCC control reg,
+ * to avoid reading additional data from the DCC data reg
+ */
+ if (size == 1)
+ buf_set_u32(fields[1].out_value, 0, 5,
+ eice_regs[EICE_COMMS_CTRL].addr);
+
+ fields[0].in_value = (uint8_t *)data;
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
+ jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
+
+ data++;
+ size--;
+ }
+
+ return jtag_execute_queue();
+}
+
+/**
+ * Queue a read for an EmbeddedICE register into the register cache,
+ * not checking the value read.
+ */