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flash/nor/nrf5: remove is_erased setting and autoerase before write
[fw/openocd]
/
src
/
target
/
embeddedice.c
diff --git
a/src/target/embeddedice.c
b/src/target/embeddedice.c
index abc49d7e6f729302db93f454f3e9e44de5420eaa..7232ef1e4685ab9b0e07d143576e9d397208f27e 100644
(file)
--- a/
src/target/embeddedice.c
+++ b/
src/target/embeddedice.c
@@
-19,16
+19,16
@@
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "embeddedice.h"
#include "register.h"
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "embeddedice.h"
#include "register.h"
+#include <helper/time_support.h>
/**
* @file
/**
* @file
@@
-53,9
+53,9
@@
static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf);
* From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
*/
static const struct {
* From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
*/
static const struct {
- c
har
*name;
- unsigned short
addr;
- unsigned short
width;
+ c
onst char
*name;
+ unsigned short addr;
+ unsigned short width;
} eice_regs[] = {
[EICE_DBG_CTRL] = {
.name = "debug_ctrl",
} eice_regs[] = {
[EICE_DBG_CTRL] = {
.name = "debug_ctrl",
@@
-87,7
+87,7
@@
static const struct {
.addr = 9,
.width = 32,
},
.addr = 9,
.width = 32,
},
- [EICE_W0_DATA_VALUE
] = {
+ [EICE_W0_DATA_VALUE] = {
.name = "watch_0_data_value",
.addr = 10,
.width = 32,
.name = "watch_0_data_value",
.addr = 10,
.width = 32,
@@
-145,14
+145,16
@@
static const struct {
},
};
},
};
-
static int embeddedice_get_reg(struct reg *reg)
{
static int embeddedice_get_reg(struct reg *reg)
{
- int retval;
-
- if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
+ int retval = embeddedice_read_reg(reg);
+ if (retval != ERROR_OK) {
LOG_ERROR("error queueing EmbeddedICE register read");
LOG_ERROR("error queueing EmbeddedICE register read");
- else if ((retval = jtag_execute_queue()) != ERROR_OK)
+ return retval;
+ }
+
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
LOG_ERROR("EmbeddedICE register read failed");
return retval;
LOG_ERROR("EmbeddedICE register read failed");
return retval;
@@
-168,8
+170,8
@@
static const struct reg_arch_type eice_reg_type = {
* Different versions of the modules have different capabilities, such as
* hardware support for vector_catch, single stepping, and monitor mode.
*/
* Different versions of the modules have different capabilities, such as
* hardware support for vector_catch, single stepping, and monitor mode.
*/
-struct reg_cache *
-
embeddedice_build_reg_cache(struct target *target,
struct arm7_9_common *arm7_9)
+struct reg_cache *
embeddedice_build_reg_cache(struct target *target,
+
struct arm7_9_common *arm7_9)
{
int retval;
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
{
int retval;
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
@@
-200,8
+202,7
@@
embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
*/
/* set up registers */
*/
/* set up registers */
- for (i = 0; i < num_regs; i++)
- {
+ for (i = 0; i < num_regs; i++) {
reg_list[i].name = eice_regs[i].name;
reg_list[i].size = eice_regs[i].width;
reg_list[i].dirty = 0;
reg_list[i].name = eice_regs[i].name;
reg_list[i].size = eice_regs[i].width;
reg_list[i].dirty = 0;
@@
-215,12
+216,10
@@
embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
/* identify EmbeddedICE version by reading DCC control register */
embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
/* identify EmbeddedICE version by reading DCC control register */
embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
+ retval = jtag_execute_queue();
+
if (retval != ERROR_OK)
{
for (i = 0; i < num_regs; i++)
for (i = 0; i < num_regs; i++)
- {
free(reg_list[i].value);
free(reg_list[i].value);
- }
free(reg_list);
free(reg_cache);
free(arch_info);
free(reg_list);
free(reg_cache);
free(arch_info);
@@
-230,8
+229,7
@@
embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
LOG_INFO("Embedded ICE version %d", eice_version);
eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
LOG_INFO("Embedded ICE version %d", eice_version);
- switch (eice_version)
- {
+ switch (eice_version) {
case 1:
/* ARM7TDMI r3, ARM7TDMI-S r3
*
case 1:
/* ARM7TDMI r3, ARM7TDMI-S r3
*
@@
-290,7
+288,7
@@
embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
* and do the appropriate setup itself.
*/
if (strcmp(target_type_name(target), "feroceon") == 0 ||
* and do the appropriate setup itself.
*/
if (strcmp(target_type_name(target), "feroceon") == 0 ||
- strcmp(target_type_name(target), "dragonite") == 0)
+
strcmp(target_type_name(target), "dragonite") == 0)
break;
LOG_ERROR("unknown EmbeddedICE version "
"(comms ctrl: 0x%8.8" PRIx32 ")",
break;
LOG_ERROR("unknown EmbeddedICE version "
"(comms ctrl: 0x%8.8" PRIx32 ")",
@@
-318,12
+316,12
@@
int embeddedice_setup(struct target *target)
* that manages break requests. ARM's "Angel Debug Monitor" is one
* common example of such code.
*/
* that manages break requests. ARM's "Angel Debug Monitor" is one
* common example of such code.
*/
- if (arm7_9->has_monitor_mode)
- {
+ if (arm7_9->has_monitor_mode) {
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
embeddedice_read_reg(dbg_ctrl);
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
embeddedice_read_reg(dbg_ctrl);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
return retval;
buf_set_u32(dbg_ctrl->value, 4, 1, 0);
embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
return retval;
buf_set_u32(dbg_ctrl->value, 4, 1, 0);
embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
@@
-350,7
+348,8
@@
int embeddedice_read_reg_w_check(struct reg *reg,
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(ice_reg->jtag_info->tap,
+ ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
@@
-415,7
+414,7
@@
int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info
->tap
, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
@@
-435,8
+434,7
@@
int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
- while (size > 0)
- {
+ while (size > 0) {
/* when reading the last item, set the register address to the DCC control reg,
* to avoid reading additional data from the DCC data reg
*/
/* when reading the last item, set the register address to the DCC control reg,
* to avoid reading additional data from the DCC data reg
*/
@@
-486,7
+484,8
@@
static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
int retval;
embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
int retval;
embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
- if ((retval = jtag_execute_queue()) != ERROR_OK)
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
LOG_ERROR("register write failed");
return retval;
}
LOG_ERROR("register write failed");
return retval;
}
@@
-497,13
+496,12
@@
static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
void embeddedice_write_reg(struct reg *reg, uint32_t value)
{
struct embeddedice_reg *ice_reg = reg->arch_info;
void embeddedice_write_reg(struct reg *reg, uint32_t value)
{
struct embeddedice_reg *ice_reg = reg->arch_info;
- int retval;
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
-
retval =
arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
+ arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
-
retval = arm_jtag_set_instr(ice_reg->jtag_info
, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+
arm_jtag_set_instr(ice_reg->jtag_info->tap
, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
uint8_t reg_addr = ice_reg->addr & 0x1f;
embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
uint8_t reg_addr = ice_reg->addr & 0x1f;
embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
@@
-537,7
+535,7
@@
int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info
->tap
, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
@@
-556,8
+554,7
@@
int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
fields[2].in_value = NULL;
fields[2].in_value = NULL;
- while (size > 0)
- {
+ while (size > 0) {
buf_set_u32(field0_out, 0, 32, *data);
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
buf_set_u32(field0_out, 0, 32, *data);
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@
-580,20
+577,22
@@
int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
uint8_t field2_out[1];
int retval;
uint32_t hsact;
uint8_t field2_out[1];
int retval;
uint32_t hsact;
- struct timeval lap;
struct timeval now;
struct timeval now;
+ struct timeval timeout_end;
if (hsbit == EICE_COMM_CTRL_WBIT)
hsact = 1;
else if (hsbit == EICE_COMM_CTRL_RBIT)
hsact = 0;
if (hsbit == EICE_COMM_CTRL_WBIT)
hsact = 1;
else if (hsbit == EICE_COMM_CTRL_RBIT)
hsact = 0;
- else
- return ERROR_INVALID_ARGUMENTS;
+ else {
+ LOG_ERROR("Invalid arguments");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info
->tap
, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
@@
-612,19
+611,21
@@
int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
fields[2].in_value = NULL;
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
fields[2].in_value = NULL;
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
- gettimeofday(&lap, NULL);
+ gettimeofday(&timeout_end, NULL);
+ timeval_add_time(&timeout_end, 0, timeout * 1000);
do {
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
do {
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
return retval;
if (buf_get_u32(field0_in, hsbit, 1) == hsact)
return ERROR_OK;
gettimeofday(&now, NULL);
return retval;
if (buf_get_u32(field0_in, hsbit, 1) == hsact)
return ERROR_OK;
gettimeofday(&now, NULL);
- } while ((uint32_t)((now.tv_sec - lap.tv_sec) * 1000
- + (now.tv_usec - lap.tv_usec) / 1000) <= timeout);
+ } while (timeval_compare(&now, &timeout_end) <= 0);
+ LOG_ERROR("embeddedice handshake timeout");
return ERROR_TARGET_TIMEOUT;
}
return ERROR_TARGET_TIMEOUT;
}
@@
-633,12
+634,11
@@
int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
* This is an inner loop of the open loop DCC write of data to target
*/
void embeddedice_write_dcc(struct jtag_tap *tap,
* This is an inner loop of the open loop DCC write of data to target
*/
void embeddedice_write_dcc(struct jtag_tap *tap,
- int reg_addr, uint8_t *buffer, int little, int count)
+ int reg_addr,
const
uint8_t *buffer, int little, int count)
{
int i;
{
int i;
- for (i = 0; i < count; i++)
- {
+ for (i = 0; i < count; i++) {
embeddedice_write_reg_inner(tap, reg_addr,
fast_target_buffer_get_u32(buffer, little));
buffer += 4;
embeddedice_write_reg_inner(tap, reg_addr,
fast_target_buffer_get_u32(buffer, little));
buffer += 4;