-static int embeddedice_reg_arch_info[] =
-{
- 0x0, 0x1, 0x4, 0x5,
- 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
- 0x2
+/*
+ * From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
+ */
+static const struct {
+ char *name;
+ unsigned short addr;
+ unsigned short width;
+} eice_regs[] = {
+ [EICE_DBG_CTRL] = {
+ .name = "debug_ctrl",
+ .addr = 0,
+ /* width is assigned based on EICE version */
+ },
+ [EICE_DBG_STAT] = {
+ .name = "debug_status",
+ .addr = 1,
+ /* width is assigned based on EICE version */
+ },
+ [EICE_COMMS_CTRL] = {
+ .name = "comms_ctrl",
+ .addr = 4,
+ .width = 6,
+ },
+ [EICE_COMMS_DATA] = {
+ .name = "comms_data",
+ .addr = 5,
+ .width = 32,
+ },
+ [EICE_W0_ADDR_VALUE] = {
+ .name = "watch_0_addr_value",
+ .addr = 8,
+ .width = 32,
+ },
+ [EICE_W0_ADDR_MASK] = {
+ .name = "watch_0_addr_mask",
+ .addr = 9,
+ .width = 32,
+ },
+ [EICE_W0_DATA_VALUE ] = {
+ .name = "watch_0_data_value",
+ .addr = 10,
+ .width = 32,
+ },
+ [EICE_W0_DATA_MASK] = {
+ .name = "watch_0_data_mask",
+ .addr = 11,
+ .width = 32,
+ },
+ [EICE_W0_CONTROL_VALUE] = {
+ .name = "watch_0_control_value",
+ .addr = 12,
+ .width = 9,
+ },
+ [EICE_W0_CONTROL_MASK] = {
+ .name = "watch_0_control_mask",
+ .addr = 13,
+ .width = 8,
+ },
+ [EICE_W1_ADDR_VALUE] = {
+ .name = "watch_1_addr_value",
+ .addr = 16,
+ .width = 32,
+ },
+ [EICE_W1_ADDR_MASK] = {
+ .name = "watch_1_addr_mask",
+ .addr = 17,
+ .width = 32,
+ },
+ [EICE_W1_DATA_VALUE] = {
+ .name = "watch_1_data_value",
+ .addr = 18,
+ .width = 32,
+ },
+ [EICE_W1_DATA_MASK] = {
+ .name = "watch_1_data_mask",
+ .addr = 19,
+ .width = 32,
+ },
+ [EICE_W1_CONTROL_VALUE] = {
+ .name = "watch_1_control_value",
+ .addr = 20,
+ .width = 9,
+ },
+ [EICE_W1_CONTROL_MASK] = {
+ .name = "watch_1_control_mask",
+ .addr = 21,
+ .width = 8,
+ },
+ /* vector_catch isn't always present */
+ [EICE_VEC_CATCH] = {
+ .name = "vector_catch",
+ .addr = 2,
+ .width = 8,
+ },