+ retval = dsp5680xx_convert_address(&address, &pmem);
+ err_check_propagate(retval);
+
+ dsp5680xx_context.flush = 0;
+ int counter = FLUSH_COUNT_READ_WRITE;
+
+ for (unsigned i = 0; i < count; i++) {
+ if (--counter == 0) {
+ dsp5680xx_context.flush = 1;
+ counter = FLUSH_COUNT_READ_WRITE;
+ }
+ switch (size) {
+ case 1:
+ if (!(i % 2))
+ retval =
+ dsp5680xx_read_16_single(target,
+ address + i / 2,
+ buffer + i, pmem);
+ break;
+ case 2:
+ retval =
+ dsp5680xx_read_16_single(target, address + i,
+ buffer + 2 * i, pmem);
+ break;
+ case 4:
+ retval =
+ dsp5680xx_read_32_single(target, address + 2 * i,
+ buffer + 4 * i, pmem);
+ break;
+ default:
+ LOG_USER("%s: Invalid read size.", __func__);
+ break;
+ }
+ err_check_propagate(retval);
+ dsp5680xx_context.flush = 0;
+ }
+
+ dsp5680xx_context.flush = 1;
+ retval = dsp5680xx_execute_queue();
+ err_check_propagate(retval);
+
+ return retval;
+}
+
+static int dsp5680xx_write_16_single(struct target *t, uint32_t a,
+ uint16_t data, uint8_t w_pmem)
+{
+ struct target *target = t;
+
+ uint32_t address = a;
+
+ int retval = 0;
+
+ retval = core_move_long_to_r0(target, address);
+ err_check_propagate(retval);
+ if (w_pmem) {
+ retval = core_move_value_to_y0(target, data);
+ err_check_propagate(retval);
+ retval = core_move_y0_at_pr0_inc(target);
+ err_check_propagate(retval);
+ } else {
+ retval = core_move_value_at_r0(target, data);
+ err_check_propagate(retval);
+ }
+ return retval;
+}
+
+static int dsp5680xx_write_32_single(struct target *t, uint32_t a,
+ uint32_t data, int w_pmem)
+{
+ struct target *target = t;
+
+ uint32_t address = a;
+
+ int retval = ERROR_OK;
+
+ retval = core_move_long_to_r0(target, address);
+ err_check_propagate(retval);
+ retval = core_move_long_to_y(target, data);
+ err_check_propagate(retval);
+ if (w_pmem)
+ retval = core_move_y0_at_pr0_inc(target);
+ else
+ retval = core_move_y0_at_r0_inc(target);
+ err_check_propagate(retval);
+ if (w_pmem)
+ retval = core_move_y1_at_pr0_inc(target);
+ else
+ retval = core_move_y1_at_r0_inc(target);
+ err_check_propagate(retval);
+ return retval;
+}
+
+static int dsp5680xx_write_8(struct target *t, uint32_t a, uint32_t c,
+ const uint8_t *d, int pmem)
+{
+ struct target *target = t;
+
+ uint32_t address = a;
+
+ uint32_t count = c;
+
+ const uint8_t *data = d;
+
+ int retval = 0;
+
+ uint16_t data_16;
+
+ uint32_t iter;
+
+ int counter = FLUSH_COUNT_READ_WRITE;
+
+ for (iter = 0; iter < count / 2; iter++) {
+ if (--counter == 0) {
+ dsp5680xx_context.flush = 1;
+ counter = FLUSH_COUNT_READ_WRITE;
+ }
+ data_16 = (data[2 * iter] | (data[2 * iter + 1] << 8));
+ retval =
+ dsp5680xx_write_16_single(target, address + iter, data_16,
+ pmem);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("%s: Could not write to p:0x%04" PRIX32, __func__,
+ address);
+ dsp5680xx_context.flush = 1;
+ return retval;
+ }
+ dsp5680xx_context.flush = 0;
+ }
+ dsp5680xx_context.flush = 1;
+
+ /* Only one byte left, let's not overwrite the other byte (mem is 16bit) */
+ /* Need to retrieve the part we do not want to overwrite. */
+ uint16_t data_old;
+
+ if ((count == 1) || (count % 2)) {
+ retval =
+ dsp5680xx_read(target, address + iter, 1, 1,
+ (uint8_t *) &data_old);
+ err_check_propagate(retval);
+ if (count == 1)
+ data_old = (((data_old & 0xff) << 8) | data[0]); /* preserve upper byte */
+ else
+ data_old =
+ (((data_old & 0xff) << 8) | data[2 * iter + 1]);
+ retval =
+ dsp5680xx_write_16_single(target, address + iter, data_old,
+ pmem);
+ err_check_propagate(retval);
+ }
+ return retval;
+}
+
+static int dsp5680xx_write_16(struct target *t, uint32_t a, uint32_t c,
+ const uint8_t *d, int pmem)
+{
+ struct target *target = t;
+
+ uint32_t address = a;
+
+ uint32_t count = c;
+
+ const uint8_t *data = d;
+
+ int retval = ERROR_OK;
+
+ uint32_t iter;
+
+ int counter = FLUSH_COUNT_READ_WRITE;
+
+ for (iter = 0; iter < count; iter++) {
+ if (--counter == 0) {
+ dsp5680xx_context.flush = 1;
+ counter = FLUSH_COUNT_READ_WRITE;
+ }
+ retval =
+ dsp5680xx_write_16_single(target, address + iter,
+ data[iter], pmem);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("%s: Could not write to p:0x%04" PRIX32, __func__,
+ address);
+ dsp5680xx_context.flush = 1;
+ return retval;
+ }
+ dsp5680xx_context.flush = 0;
+ }
+ dsp5680xx_context.flush = 1;
+ return retval;
+}
+
+static int dsp5680xx_write_32(struct target *t, uint32_t a, uint32_t c,
+ const uint8_t *d, int pmem)
+{
+ struct target *target = t;
+
+ uint32_t address = a;
+
+ uint32_t count = c;
+
+ const uint8_t *data = d;
+
+ int retval = ERROR_OK;
+
+ uint32_t iter;
+
+ int counter = FLUSH_COUNT_READ_WRITE;
+
+ for (iter = 0; iter < count; iter++) {
+ if (--counter == 0) {
+ dsp5680xx_context.flush = 1;
+ counter = FLUSH_COUNT_READ_WRITE;
+ }
+ retval =
+ dsp5680xx_write_32_single(target, address + (iter << 1),
+ data[iter], pmem);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("%s: Could not write to p:0x%04" PRIX32, __func__,
+ address);
+ dsp5680xx_context.flush = 1;
+ return retval;
+ }
+ dsp5680xx_context.flush = 0;
+ }
+ dsp5680xx_context.flush = 1;
+ return retval;
+}
+
+/**
+ * Writes @buffer to memory.
+ * The parameter @address determines whether @buffer should be written to
+ * P: (program) memory or X: (dat) memory.
+ *
+ * @param target
+ * @param address
+ * @param size Bytes (1), Half words (2), Words (4).
+ * @param count In bytes.
+ * @param buffer
+ *
+ * @return
+ */
+static int dsp5680xx_write(struct target *t, target_addr_t a, uint32_t s, uint32_t c,
+ const uint8_t *b)
+{
+ /* TODO Cannot write 32bit to odd address, will write 0x12345678 as 0x5678 0x0012 */
+ struct target *target = t;
+
+ uint32_t address = a;
+
+ uint32_t count = c;
+
+ uint8_t const *buffer = b;
+
+ uint32_t size = s;
+
+ check_halt_and_debug(target);
+
+ int retval = 0;
+
+ int p_mem = 1;
+
+ retval = dsp5680xx_convert_address(&address, &p_mem);
+ err_check_propagate(retval);
+
+ switch (size) {
+ case 1:
+ retval =
+ dsp5680xx_write_8(target, address, count, buffer, p_mem);
+ break;
+ case 2:
+ retval =
+ dsp5680xx_write_16(target, address, count, buffer, p_mem);
+ break;
+ case 4:
+ retval =
+ dsp5680xx_write_32(target, address, count, buffer, p_mem);
+ break;
+ default:
+ retval = ERROR_TARGET_DATA_ABORT;
+ err_check(retval, DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT,
+ "Invalid data size.");
+ break;
+ }
+ return retval;
+}
+
+static int dsp5680xx_write_buffer(struct target *t, target_addr_t a, uint32_t size,
+ const uint8_t *b)
+{
+ check_halt_and_debug(t);
+ return dsp5680xx_write(t, a, 1, size, b);
+}
+
+/**
+ * This function is called by verify_image, it is used to read data from memory.
+ *
+ * @param target
+ * @param address Word addressing.
+ * @param size In bytes.
+ * @param buffer
+ *
+ * @return
+ */
+static int dsp5680xx_read_buffer(struct target *t, target_addr_t a, uint32_t size,
+ uint8_t *buf)
+{
+ check_halt_and_debug(t);
+ /* The "/2" solves the byte/word addressing issue.*/
+ return dsp5680xx_read(t, a, 2, size / 2, buf);
+}
+
+/**
+ * This function is not implemented.
+ * It returns an error in order to get OpenOCD to do read out the data
+ * and calculate the CRC, or try a binary comparison.
+ *
+ * @param target
+ * @param address Start address of the image.
+ * @param size In bytes.
+ * @param checksum
+ *
+ * @return
+ */
+static int dsp5680xx_checksum_memory(struct target *t, target_addr_t a, uint32_t s,
+ uint32_t *checksum)
+{
+ return ERROR_FAIL;
+}
+
+/**
+ * Calculates a signature over @word_count words in the data from @buff16.
+ * The algorithm used is the same the FM uses, so the @return may be used to compare
+ * with the one generated by the FM module, and check if flashing was successful.
+ * This algorithm is based on the perl script available from the Freescale website at FAQ 25630.
+ *
+ * @param buff16
+ * @param word_count
+ *
+ * @return
+ */
+static int perl_crc(const uint8_t *buff8, uint32_t word_count)
+{
+ uint16_t checksum = 0xffff;
+
+ uint16_t data, fbmisr;
+
+ uint32_t i;
+
+ for (i = 0; i < word_count; i++) {
+ data = (buff8[2 * i] | (buff8[2 * i + 1] << 8));
+ fbmisr =
+ (checksum & 2) >> 1 ^ (checksum & 4) >> 2 ^ (checksum & 16)
+ >> 4 ^ (checksum & 0x8000) >> 15;
+ checksum = (data ^ ((checksum << 1) | fbmisr));
+ }
+ i--;
+ for (; !(i & 0x80000000); i--) {
+ data = (buff8[2 * i] | (buff8[2 * i + 1] << 8));
+ fbmisr =
+ (checksum & 2) >> 1 ^ (checksum & 4) >> 2 ^ (checksum & 16)
+ >> 4 ^ (checksum & 0x8000) >> 15;
+ checksum = (data ^ ((checksum << 1) | fbmisr));
+ }
+ return checksum;
+}
+
+/**
+ * Resets the SIM. (System Integration Modul).
+ *
+ * @param target
+ *
+ * @return
+ */
+int dsp5680xx_f_SIM_reset(struct target *target)
+{
+ int retval = ERROR_OK;
+
+ uint16_t sim_cmd = SIM_CMD_RESET;
+
+ uint32_t sim_addr;
+
+ if (strcmp(target->tap->chip, "dsp568013") == 0) {
+ sim_addr = MC568013_SIM_BASE_ADDR + S_FILE_DATA_OFFSET;
+ retval =
+ dsp5680xx_write(target, sim_addr, 1, 2,
+ (const uint8_t *)&sim_cmd);
+ err_check_propagate(retval);
+ }
+ return retval;
+}
+
+/**
+ * Halts the core and resets the SIM. (System Integration Modul).
+ *
+ * @param target
+ *
+ * @return
+ */
+static int dsp5680xx_soft_reset_halt(struct target *target)
+{
+ /* TODO is this what this function is expected to do...? */
+ int retval;
+
+ retval = dsp5680xx_halt(target);
+ err_check_propagate(retval);
+ retval = dsp5680xx_f_SIM_reset(target);
+ err_check_propagate(retval);
+ return retval;
+}
+
+int dsp5680xx_f_protect_check(struct target *target, uint16_t *protected)
+{
+ int retval;
+
+ check_halt_and_debug(target);
+ if (protected == NULL) {
+ const char *msg = "NULL pointer not valid.";
+
+ err_check(ERROR_FAIL,
+ DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS, msg);
+ }
+ retval =
+ dsp5680xx_read_16_single(target, HFM_BASE_ADDR | HFM_PROT,
+ (uint8_t *) protected, 0);
+ err_check_propagate(retval);
+ return retval;
+}
+
+/**
+ * Executes a command on the FM module.
+ * Some commands use the parameters @address and @data, others ignore them.
+ *
+ * @param target
+ * @param command Command to execute.
+ * @param address Command parameter.
+ * @param data Command parameter.
+ * @param hfm_ustat FM status register.
+ * @param pmem Address is P: (program) memory (@pmem == 1) or X: (dat) memory (@pmem == 0)
+ *
+ * @return
+ */
+static int dsp5680xx_f_ex(struct target *t, uint16_t c, uint32_t a, uint32_t d,
+ uint16_t *h, int p)
+{
+ struct target *target = t;
+
+ uint32_t command = c;
+
+ uint32_t address = a;
+
+ uint32_t data = d;
+
+ uint16_t *hfm_ustat = h;
+
+ int pmem = p;
+
+ int retval;
+
+ retval = core_load_TX_RX_high_addr_to_r0(target);
+ err_check_propagate(retval);
+ retval = core_move_long_to_r2(target, HFM_BASE_ADDR);
+ err_check_propagate(retval);
+ uint8_t i[2];
+
+ int watchdog = 100;
+
+ do {
+ retval = core_move_at_r2_disp_to_y0(target, HFM_USTAT); /* read HMF_USTAT */
+ err_check_propagate(retval);
+ retval = core_move_y0_at_r0(target);
+ err_check_propagate(retval);
+ retval = core_rx_upper_data(target, i);
+ err_check_propagate(retval);
+ if ((watchdog--) == 1) {
+ retval = ERROR_TARGET_FAILURE;
+ const char *msg =
+ "Timed out waiting for FM to finish old command.";
+ err_check(retval, DSP5680XX_ERROR_FM_BUSY, msg);
+ }
+ } while (!(i[0] & 0x40)); /* wait until current command is complete */
+
+ dsp5680xx_context.flush = 0;
+
+ /* write to HFM_CNFG (lock=0,select bank) - flash_desc.bank&0x03, 0x01 == 0x00, 0x01 ??? */
+ retval = core_move_value_at_r2_disp(target, 0x00, HFM_CNFG);
+ err_check_propagate(retval);
+ /* write to HMF_USTAT, clear PVIOL, ACCERR &BLANK bits */
+ retval = core_move_value_at_r2_disp(target, 0x04, HFM_USTAT);
+ err_check_propagate(retval);
+ /* clear only one bit at a time */
+ retval = core_move_value_at_r2_disp(target, 0x10, HFM_USTAT);
+ err_check_propagate(retval);
+ retval = core_move_value_at_r2_disp(target, 0x20, HFM_USTAT);
+ err_check_propagate(retval);
+ /* write to HMF_PROT, clear protection */
+ retval = core_move_value_at_r2_disp(target, 0x00, HFM_PROT);
+ err_check_propagate(retval);
+ /* write to HMF_PROTB, clear protection */
+ retval = core_move_value_at_r2_disp(target, 0x00, HFM_PROTB);
+ err_check_propagate(retval);
+ retval = core_move_value_to_y0(target, data);
+ err_check_propagate(retval);
+ /* write to the flash block */
+ retval = core_move_long_to_r3(target, address);
+ err_check_propagate(retval);
+ if (pmem) {
+ retval = core_move_y0_at_pr3_inc(target);
+ err_check_propagate(retval);
+ } else {
+ retval = core_move_y0_at_r3(target);
+ err_check_propagate(retval);
+ }
+ /* write command to the HFM_CMD reg */
+ retval = core_move_value_at_r2_disp(target, command, HFM_CMD);
+ err_check_propagate(retval);
+ /* start the command */
+ retval = core_move_value_at_r2_disp(target, 0x80, HFM_USTAT);
+ err_check_propagate(retval);
+
+ dsp5680xx_context.flush = 1;
+ retval = dsp5680xx_execute_queue();
+ err_check_propagate(retval);
+
+ watchdog = 100;
+ do {
+ /* read HMF_USTAT */
+ retval = core_move_at_r2_disp_to_y0(target, HFM_USTAT);
+ err_check_propagate(retval);
+ retval = core_move_y0_at_r0(target);
+ err_check_propagate(retval);
+ retval = core_rx_upper_data(target, i);
+ err_check_propagate(retval);
+ if ((watchdog--) == 1) {
+ retval = ERROR_TARGET_FAILURE;
+ err_check(retval, DSP5680XX_ERROR_FM_CMD_TIMED_OUT,
+ "FM execution did not finish.");
+ }
+ } while (!(i[0] & 0x40)); /* wait until the command is complete */
+ *hfm_ustat = ((i[0] << 8) | (i[1]));
+ if (i[0] & HFM_USTAT_MASK_PVIOL_ACCER) {
+ retval = ERROR_TARGET_FAILURE;
+ const char *msg =
+ "pviol and/or accer bits set. HFM command execution error";
+ err_check(retval, DSP5680XX_ERROR_FM_EXEC, msg);
+ }
+ return ERROR_OK;
+}
+
+/**
+ * Prior to the execution of any Flash module command, the Flash module Clock Divider (CLKDIV) register must be initialized. The values of this register determine the speed of the internal Flash Clock (FCLK). FCLK must be in the range of 150kHz ≤ FCLK ≤ 200kHz for proper operation of the Flash module. (Running FCLK too slowly wears out the module, while running it too fast under programs Flash leading to bit errors.)
+ *
+ * @param target
+ *
+ * @return
+ */
+static int set_fm_ck_div(struct target *target)
+{
+ uint8_t i[2];
+
+ int retval;
+
+ retval = core_move_long_to_r2(target, HFM_BASE_ADDR);
+ err_check_propagate(retval);
+ retval = core_load_TX_RX_high_addr_to_r0(target);
+ err_check_propagate(retval);
+ /* read HFM_CLKD */
+ retval = core_move_at_r2_to_y0(target);
+ err_check_propagate(retval);
+ retval = core_move_y0_at_r0(target);
+ err_check_propagate(retval);
+ retval = core_rx_upper_data(target, i);
+ err_check_propagate(retval);
+ unsigned int hfm_at_wrong_value = 0;
+
+ if ((i[0] & 0x7f) != HFM_CLK_DEFAULT) {
+ LOG_DEBUG("HFM CLK divisor contained incorrect value (0x%02X).",
+ i[0] & 0x7f);
+ hfm_at_wrong_value = 1;
+ } else {
+ LOG_DEBUG
+ ("HFM CLK divisor was already set to correct value (0x%02X).",
+ i[0] & 0x7f);
+ return ERROR_OK;
+ }
+ /* write HFM_CLKD */
+ retval = core_move_value_at_r2(target, HFM_CLK_DEFAULT);
+ err_check_propagate(retval);
+ /* verify HFM_CLKD */
+ retval = core_move_at_r2_to_y0(target);
+ err_check_propagate(retval);
+ retval = core_move_y0_at_r0(target);
+ err_check_propagate(retval);
+ retval = core_rx_upper_data(target, i);
+ err_check_propagate(retval);
+ if (i[0] != (0x80 | (HFM_CLK_DEFAULT & 0x7f))) {
+ retval = ERROR_TARGET_FAILURE;
+ err_check(retval, DSP5680XX_ERROR_FM_SET_CLK,
+ "Unable to set HFM CLK divisor.");
+ }
+ if (hfm_at_wrong_value)
+ LOG_DEBUG("HFM CLK divisor set to 0x%02x.", i[0] & 0x7f);
+ return ERROR_OK;
+}
+
+/**
+ * Executes the FM calculate signature command. The FM will calculate over the data from @address to @address + @words -1. The result is written to a register, then read out by this function and returned in @signature. The value @signature may be compared to the the one returned by perl_crc to verify the flash was written correctly.
+ *
+ * @param target
+ * @param address Start of flash array where the signature should be calculated.
+ * @param words Number of words over which the signature should be calculated.
+ * @param signature Value calculated by the FM.
+ *
+ * @return
+ */
+static int dsp5680xx_f_signature(struct target *t, uint32_t a, uint32_t words,
+ uint16_t *signature)
+{
+ struct target *target = t;
+
+ uint32_t address = a;
+
+ int retval;
+
+ uint16_t hfm_ustat;
+
+ if (!dsp5680xx_context.debug_mode_enabled) {
+ retval = eonce_enter_debug_mode_without_reset(target, NULL);
+ /*
+ * Generate error here, since it is not done in eonce_enter_debug_mode_without_reset
+ */
+ err_check(retval, DSP5680XX_ERROR_HALT,
+ "Failed to halt target.");
+ }
+ retval =
+ dsp5680xx_f_ex(target, HFM_CALCULATE_DATA_SIGNATURE, address, words,
+ &hfm_ustat, 1);
+ err_check_propagate(retval);
+ retval =
+ dsp5680xx_read_16_single(target, HFM_BASE_ADDR | HFM_DATA,
+ (uint8_t *) signature, 0);
+ return retval;
+}
+
+int dsp5680xx_f_erase_check(struct target *target, uint8_t *erased,
+ uint32_t sector)
+{
+ int retval;
+
+ uint16_t hfm_ustat;
+
+ uint32_t tmp;
+
+ if (!dsp5680xx_context.debug_mode_enabled) {
+ retval = dsp5680xx_halt(target);
+ err_check_propagate(retval);
+ }
+ retval = set_fm_ck_div(target);
+ err_check_propagate(retval);
+ /*
+ * Check if chip is already erased.
+ */
+ tmp = HFM_FLASH_BASE_ADDR + sector * HFM_SECTOR_SIZE / 2;
+ retval =
+ dsp5680xx_f_ex(target, HFM_ERASE_VERIFY, tmp, 0, &hfm_ustat, 1);
+ err_check_propagate(retval);
+ if (erased != NULL)
+ *erased = (uint8_t) (hfm_ustat & HFM_USTAT_MASK_BLANK);
+ return retval;
+}
+
+/**
+ * Executes the FM page erase command.
+ *
+ * @param target
+ * @param sector Page to erase.
+ * @param hfm_ustat FM module status register.
+ *
+ * @return
+ */
+static int erase_sector(struct target *target, int sector, uint16_t *hfm_ustat)
+{
+ int retval;
+
+ uint32_t tmp = HFM_FLASH_BASE_ADDR + sector * HFM_SECTOR_SIZE / 2;
+
+ retval = dsp5680xx_f_ex(target, HFM_PAGE_ERASE, tmp, 0, hfm_ustat, 1);
+ err_check_propagate(retval);
+ return retval;
+}
+
+/**
+ * Executes the FM mass erase command. Erases the flash array completely.
+ *
+ * @param target
+ * @param hfm_ustat FM module status register.
+ *
+ * @return
+ */
+static int mass_erase(struct target *target, uint16_t *hfm_ustat)
+{
+ int retval;
+
+ retval = dsp5680xx_f_ex(target, HFM_MASS_ERASE, 0, 0, hfm_ustat, 1);
+ return retval;
+}
+
+int dsp5680xx_f_erase(struct target *target, int first, int last)
+{
+ int retval;
+
+ if (!dsp5680xx_context.debug_mode_enabled) {
+ retval = dsp5680xx_halt(target);
+ err_check_propagate(retval);
+ }
+ /*
+ * Reset SIM
+ *
+ */
+ retval = dsp5680xx_f_SIM_reset(target);
+ err_check_propagate(retval);
+ /*
+ * Set hfmdiv
+ *
+ */
+ retval = set_fm_ck_div(target);
+ err_check_propagate(retval);
+
+ uint16_t hfm_ustat;
+
+ int do_mass_erase = ((!(first | last))
+ || ((first == 0)
+ && (last == (HFM_SECTOR_COUNT - 1))));
+ if (do_mass_erase) {
+ /* Mass erase */
+ retval = mass_erase(target, &hfm_ustat);
+ err_check_propagate(retval);
+ } else {
+ for (int i = first; i <= last; i++) {
+ retval = erase_sector(target, i, &hfm_ustat);
+ err_check_propagate(retval);
+ }
+ }
+ return ERROR_OK;
+}
+
+/*
+ * Algorithm for programming normal p: flash
+ * Follow state machine from "56F801x Peripheral Reference Manual"@163.
+ * Registers to set up before calling:
+ * r0: TX/RX high address.
+ * r2: FM module base address.
+ * r3: Destination address in flash.
+ *
+ * hfm_wait: // wait for buffer empty
+ * brclr #0x80, x:(r2+0x13), hfm_wait
+ * rx_check: // wait for input buffer full
+ * brclr #0x01, x:(r0-2), rx_check
+ * move.w x:(r0), y0 // read from Rx buffer
+ * move.w y0, p:(r3)+
+ * move.w #0x20, x:(r2+0x14) // write PGM command
+ * move.w #0x80, x:(r2+0x13) // start the command
+ * move.w X:(R2+0x13), A // Read USTAT register
+ * brclr #0x20, A, accerr_check // protection violation check
+ * bfset #0x20, X:(R2+0x13) // clear pviol
+ * bra hfm_wait
+ * accerr_check:
+ * brclr #0x10, A, hfm_wait // access error check
+ * bfset #0x10, X:(R2+0x13) // clear accerr
+ * bra hfm_wait // loop
+ * 0x00000000 0x8A460013807D brclr #0x80, X:(R2+0x13),*+0
+ * 0x00000003 0xE700 nop
+ * 0x00000004 0xE700 nop
+ * 0x00000005 0x8A44FFFE017B brclr #1, X:(R0-2),*-2
+ * 0x00000008 0xE700 nop
+ * 0x00000009 0xF514 move.w X:(R0), Y0
+ * 0x0000000A 0x8563 move.w Y0, P:(R3)+
+ * 0x0000000B 0x864600200014 move.w #32, X:(R2+0x14)
+ * 0x0000000E 0x864600800013 move.w #128, X:(R2+0x13)
+ * 0x00000011 0xF0420013 move.w X:(R2+0x13), A
+ * 0x00000013 0x8B402004 brclr #0x20, A,*+6
+ * 0x00000015 0x824600130020 bfset #0x20, X:(R2+0x13)
+ * 0x00000018 0xA967 bra *-24
+ * 0x00000019 0x8B401065 brclr #0x10, A,*-25
+ * 0x0000001B 0x824600130010 bfset #0x10, X:(R2+0x13)
+ * 0x0000001E 0xA961 bra *-30
+ */
+
+const uint16_t pgm_write_pflash[] = { 0x8A46, 0x0013, 0x807D, 0xE700,
+ 0xE700, 0x8A44, 0xFFFE, 0x017B,
+ 0xE700, 0xF514, 0x8563, 0x8646,
+ 0x0020, 0x0014, 0x8646, 0x0080,
+ 0x0013, 0xF042, 0x0013, 0x8B40,
+ 0x2004, 0x8246, 0x0013, 0x0020,
+ 0xA967, 0x8B40, 0x1065, 0x8246,
+ 0x0013, 0x0010, 0xA961
+};
+
+const uint32_t pgm_write_pflash_length = 31;
+
+int dsp5680xx_f_wr(struct target *t, const uint8_t *b, uint32_t a, uint32_t count,
+ int is_flash_lock)
+{
+ struct target *target = t;
+
+ uint32_t address = a;
+
+ const uint8_t *buffer = b;
+
+ int retval = ERROR_OK;
+
+ if (!dsp5680xx_context.debug_mode_enabled) {
+ retval = eonce_enter_debug_mode(target, NULL);
+ err_check_propagate(retval);
+ }
+ /*
+ * Download the pgm that flashes.
+ *
+ */
+ const uint32_t len = pgm_write_pflash_length;
+
+ uint32_t ram_addr = 0x8700;
+
+ /*
+ * This seems to be a safe address.
+ * This one is the one used by codewarrior in 56801x_flash.cfg
+ */
+ if (!is_flash_lock) {
+ retval =
+ dsp5680xx_write(target, ram_addr, 1, len * 2,
+ (uint8_t *) pgm_write_pflash);
+ err_check_propagate(retval);
+ retval = dsp5680xx_execute_queue();
+ err_check_propagate(retval);
+ }
+ /*
+ * Set hfmdiv
+ *
+ */
+ retval = set_fm_ck_div(target);
+ err_check_propagate(retval);
+ /*
+ * Setup registers needed by pgm_write_pflash
+ *
+ */
+
+ dsp5680xx_context.flush = 0;
+
+ retval = core_move_long_to_r3(target, address); /* Destination address to r3 */
+ err_check_propagate(retval);
+ core_load_TX_RX_high_addr_to_r0(target); /* TX/RX reg address to r0 */
+ err_check_propagate(retval);
+ retval = core_move_long_to_r2(target, HFM_BASE_ADDR); /* FM base address to r2 */
+ err_check_propagate(retval);
+ /*
+ * Run flashing program.
+ *
+ */
+ /* write to HFM_CNFG (lock=0, select bank) */
+ retval = core_move_value_at_r2_disp(target, 0x00, HFM_CNFG);
+ err_check_propagate(retval);
+ /* write to HMF_USTAT, clear PVIOL, ACCERR &BLANK bits */
+ retval = core_move_value_at_r2_disp(target, 0x04, HFM_USTAT);
+ err_check_propagate(retval);
+ /* clear only one bit at a time */
+ retval = core_move_value_at_r2_disp(target, 0x10, HFM_USTAT);
+ err_check_propagate(retval);
+ retval = core_move_value_at_r2_disp(target, 0x20, HFM_USTAT);
+ err_check_propagate(retval);
+ /* write to HMF_PROT, clear protection */
+ retval = core_move_value_at_r2_disp(target, 0x00, HFM_PROT);
+ err_check_propagate(retval);
+ /* write to HMF_PROTB, clear protection */
+ retval = core_move_value_at_r2_disp(target, 0x00, HFM_PROTB);
+ err_check_propagate(retval);
+ if (count % 2) {
+ /* TODO implement handling of odd number of words. */
+ retval = ERROR_FAIL;
+ const char *msg = "Cannot handle odd number of words.";
+
+ err_check(retval, DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT,
+ msg);
+ }
+
+ dsp5680xx_context.flush = 1;
+ retval = dsp5680xx_execute_queue();
+ err_check_propagate(retval);
+
+ uint32_t drscan_data;
+
+ uint16_t tmp = (buffer[0] | (buffer[1] << 8));
+
+ retval = core_tx_upper_data(target, tmp, &drscan_data);
+ err_check_propagate(retval);
+
+ retval = dsp5680xx_resume(target, 0, ram_addr, 0, 0);
+ err_check_propagate(retval);
+
+ int counter = FLUSH_COUNT_FLASH;
+
+ dsp5680xx_context.flush = 0;
+ uint32_t i;
+
+ for (i = 1; (i < count / 2) && (i < HFM_SIZE_WORDS); i++) {
+ if (--counter == 0) {
+ dsp5680xx_context.flush = 1;
+ counter = FLUSH_COUNT_FLASH;
+ }
+ tmp = (buffer[2 * i] | (buffer[2 * i + 1] << 8));
+ retval = core_tx_upper_data(target, tmp, &drscan_data);
+ if (retval != ERROR_OK) {
+ dsp5680xx_context.flush = 1;
+ err_check_propagate(retval);
+ }
+ dsp5680xx_context.flush = 0;
+ }
+ dsp5680xx_context.flush = 1;
+ if (!is_flash_lock) {
+ /*
+ *Verify flash (skip when exec lock sequence)
+ *
+ */
+ uint16_t signature;
+
+ uint16_t pc_crc;
+
+ retval = dsp5680xx_f_signature(target, address, i, &signature);
+ err_check_propagate(retval);
+ pc_crc = perl_crc(buffer, i);
+ if (pc_crc != signature) {
+ retval = ERROR_FAIL;
+ const char *msg =
+ "Flashed data failed CRC check, flash again!";
+ err_check(retval, DSP5680XX_ERROR_FLASHING_CRC, msg);
+ }
+ }
+ return retval;
+}
+
+int dsp5680xx_f_unlock(struct target *target)
+{
+ int retval = ERROR_OK;
+
+ uint16_t eonce_status;
+
+ uint32_t instr;
+
+ uint32_t ir_out;
+
+ struct jtag_tap *tap_chp;
+
+ struct jtag_tap *tap_cpu;
+
+ tap_chp = jtag_tap_by_string("dsp568013.chp");
+ if (tap_chp == NULL) {
+ retval = ERROR_FAIL;
+ err_check(retval, DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER,
+ "Failed to get master tap.");
+ }
+ tap_cpu = jtag_tap_by_string("dsp568013.cpu");
+ if (tap_cpu == NULL) {
+ retval = ERROR_FAIL;
+ err_check(retval, DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE,
+ "Failed to get master tap.");
+ }
+
+ retval = eonce_enter_debug_mode_without_reset(target, &eonce_status);
+ if (retval == ERROR_OK)
+ LOG_WARNING("Memory was not locked.");
+
+ jtag_add_reset(0, 1);
+ jtag_add_sleep(TIME_DIV_FREESCALE * 200 * 1000);
+
+ retval = reset_jtag();
+ err_check(retval, DSP5680XX_ERROR_JTAG_RESET,
+ "Failed to reset JTAG state machine");
+ jtag_add_sleep(150);
+
+ /* Enable core tap */
+ tap_chp->enabled = true;
+ retval = switch_tap(target, tap_chp, tap_cpu);
+ err_check_propagate(retval);
+
+ instr = JTAG_INSTR_DEBUG_REQUEST;
+ retval =
+ dsp5680xx_irscan(target, &instr, &ir_out,
+ DSP5680XX_JTAG_CORE_TAP_IRLEN);
+ err_check_propagate(retval);
+ jtag_add_sleep(TIME_DIV_FREESCALE * 100 * 1000);
+ jtag_add_reset(0, 0);
+ jtag_add_sleep(TIME_DIV_FREESCALE * 300 * 1000);
+
+ /* Enable master tap */
+ tap_chp->enabled = false;
+ retval = switch_tap(target, tap_chp, tap_cpu);
+ err_check_propagate(retval);
+
+ /* Execute mass erase to unlock */
+ instr = MASTER_TAP_CMD_FLASH_ERASE;
+ retval =
+ dsp5680xx_irscan(target, &instr, &ir_out,
+ DSP5680XX_JTAG_MASTER_TAP_IRLEN);
+ err_check_propagate(retval);
+
+ instr = HFM_CLK_DEFAULT;
+ retval = dsp5680xx_drscan(target, (uint8_t *) &instr, (uint8_t *) &ir_out, 16);
+ err_check_propagate(retval);
+
+ jtag_add_sleep(TIME_DIV_FREESCALE * 150 * 1000);
+ jtag_add_reset(0, 1);
+ jtag_add_sleep(TIME_DIV_FREESCALE * 200 * 1000);
+
+ retval = reset_jtag();
+ err_check(retval, DSP5680XX_ERROR_JTAG_RESET,
+ "Failed to reset JTAG state machine");
+ jtag_add_sleep(150);
+
+ instr = 0x0606ffff;
+ retval = dsp5680xx_drscan(target, (uint8_t *) &instr, (uint8_t *) &ir_out,
+ 32);
+ err_check_propagate(retval);
+
+ /* enable core tap */
+ instr = 0x5;
+ retval =
+ dsp5680xx_irscan(target, &instr, &ir_out,
+ DSP5680XX_JTAG_MASTER_TAP_IRLEN);
+ err_check_propagate(retval);
+ instr = 0x2;
+ retval = dsp5680xx_drscan(target, (uint8_t *) &instr, (uint8_t *) &ir_out,
+ 4);
+ err_check_propagate(retval);
+
+ tap_cpu->enabled = true;
+ tap_chp->enabled = false;
+ target->state = TARGET_RUNNING;
+ dsp5680xx_context.debug_mode_enabled = false;
+ return retval;
+}
+
+int dsp5680xx_f_lock(struct target *target)
+{
+ int retval;
+
+ struct jtag_tap *tap_chp;
+
+ struct jtag_tap *tap_cpu;
+ uint16_t lock_word[] = { HFM_LOCK_FLASH };
+ retval = dsp5680xx_f_wr(target, (uint8_t *) (lock_word), HFM_LOCK_ADDR_L, 2, 1);
+ err_check_propagate(retval);
+
+ jtag_add_reset(0, 1);
+ jtag_add_sleep(TIME_DIV_FREESCALE * 200 * 1000);
+
+ retval = reset_jtag();
+ err_check(retval, DSP5680XX_ERROR_JTAG_RESET,
+ "Failed to reset JTAG state machine");
+ jtag_add_sleep(TIME_DIV_FREESCALE * 100 * 1000);
+ jtag_add_reset(0, 0);
+ jtag_add_sleep(TIME_DIV_FREESCALE * 300 * 1000);
+
+ tap_chp = jtag_tap_by_string("dsp568013.chp");
+ if (tap_chp == NULL) {
+ retval = ERROR_FAIL;
+ err_check(retval, DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER,
+ "Failed to get master tap.");
+ }
+ tap_cpu = jtag_tap_by_string("dsp568013.cpu");
+ if (tap_cpu == NULL) {
+ retval = ERROR_FAIL;
+ err_check(retval, DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE,
+ "Failed to get master tap.");
+ }
+ target->state = TARGET_RUNNING;
+ dsp5680xx_context.debug_mode_enabled = false;
+ tap_cpu->enabled = false;
+ tap_chp->enabled = true;
+ retval = switch_tap(target, tap_chp, tap_cpu);
+ return retval;
+}
+
+static int dsp5680xx_step(struct target *target, int current, target_addr_t address,
+ int handle_breakpoints)
+{
+ err_check(ERROR_FAIL, DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP,
+ "Not implemented yet.");
+}
+
+/** Holds methods for dsp5680xx targets. */
+struct target_type dsp5680xx_target = {
+ .name = "dsp5680xx",