-* r0: TX/RX high address.
-* r2: FM module base address.
-* r3: Destination address in flash.
-*
-* hfm_wait: // wait for command to finish
-* brclr #0x40,x:(r2+0x13),hfm_wait
-* rx_check: // wait for input buffer full
-* brclr #0x01,x:(r0-2),rx_check
-* move.w x:(r0),y0 // read from Rx buffer
-* move.w y0,p:(r3)+
-* move.w #0x20,x:(r2+0x14) // write PGM command
-* move.w #0x80,x:(r2+0x13) // start the command
-* brclr #0x20,X:(R2+0x13),accerr_check // protection violation check
-* bfset #0x20,X:(R2+0x13) // clear pviol
-* bra hfm_wait
-* accerr_check:
-* brclr #0x10,X:(R2+0x13),hfm_wait // access error check
-* bfset #0x10,X:(R2+0x13) // clear accerr
-* bra hfm_wait // loop
-*0x00000073 0x8A460013407D brclr #0x40,X:(R2+0x13),*+0
-*0x00000076 0xE700 nop
-*0x00000077 0xE700 nop
-*0x00000078 0x8A44FFFE017B brclr #1,X:(R0-2),*-2
-*0x0000007B 0xE700 nop
-*0x0000007C 0xF514 move.w X:(R0),Y0
-*0x0000007D 0x8563 move.w Y0,P:(R3)+
-*0x0000007E 0x864600200014 move.w #0x20,X:(R2+0x14)
-*0x00000081 0x864600800013 move.w #0x80,X:(R2+0x13)
-*0x00000084 0x8A4600132004 brclr #0x20,X:(R2+0x13),*+7
-*0x00000087 0x824600130020 bfset #0x20,X:(R2+0x13)
-*0x0000008A 0xA968 bra *-23
-*0x0000008B 0x8A4600131065 brclr #0x10,X:(R2+0x13),*-24
-*0x0000008E 0x824600130010 bfset #0x10,X:(R2+0x13)
-*0x00000091 0xA961 bra *-30
-*/
-const uint16_t pgm_write_pflash[] = {0x8A46,0x0013,0x407D,0xE700,0xE700,0x8A44,0xFFFE,0x017B,0xE700,0xF514,0x8563,0x8646,0x0020,0x0014,0x8646,0x0080,0x0013,0x8A46,0x0013,0x2004,0x8246,0x0013,0x0020,0xA968,0x8A46,0x0013,0x1065,0x8246,0x0013,0x0010,0xA961};
-const uint32_t pgm_write_pflash_length = 31;
-
-int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock){
- int retval = ERROR_OK;
- if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
- retval = eonce_enter_debug_mode(target,NULL);
- err_check_propagate(retval);
- }
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- // Download the pgm that flashes.
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- uint32_t my_favourite_ram_address = 0x8700; // This seems to be a safe address. This one is the one used by codewarrior in 56801x_flash.cfg
- if(!is_flash_lock){
- retval = dsp5680xx_write(target, my_favourite_ram_address, 1, pgm_write_pflash_length*2,(uint8_t *) pgm_write_pflash);
- err_check_propagate(retval);
- retval = dsp5680xx_execute_queue();
- err_check_propagate(retval);
- }
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- // Set hfmdiv
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- retval = set_fm_ck_div(target);
- err_check_propagate(retval);
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- // Setup registers needed by pgm_write_pflash
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-
- dsp5680xx_context.flush = 0;
-
- retval = core_move_long_to_r3(target,address); // Destination address to r3
- err_check_propagate(retval);
- core_load_TX_RX_high_addr_to_r0(target); // TX/RX reg address to r0
- err_check_propagate(retval);
- retval = core_move_long_to_r2(target,HFM_BASE_ADDR);// FM base address to r2
- err_check_propagate(retval);
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- // Run flashing program.
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- retval = core_move_value_at_r2_disp(target,0x00,HFM_CNFG); // write to HFM_CNFG (lock=0, select bank)
- err_check_propagate(retval);
- retval = core_move_value_at_r2_disp(target,0x04,HFM_USTAT);// write to HMF_USTAT, clear PVIOL, ACCERR & BLANK bits
- err_check_propagate(retval);
- retval = core_move_value_at_r2_disp(target,0x10,HFM_USTAT);// clear only one bit at a time
- err_check_propagate(retval);
- retval = core_move_value_at_r2_disp(target,0x20,HFM_USTAT);
- err_check_propagate(retval);
- retval = core_move_value_at_r2_disp(target,0x00,HFM_PROT);// write to HMF_PROT, clear protection
- err_check_propagate(retval);
- retval = core_move_value_at_r2_disp(target,0x00,HFM_PROTB);// write to HMF_PROTB, clear protection
- err_check_propagate(retval);
- if(count%2){
- //TODO implement handling of odd number of words.
- retval = ERROR_FAIL;
- err_check(retval,"Cannot handle odd number of words.");
- }
-
- dsp5680xx_context.flush = 1;
- retval = dsp5680xx_execute_queue();
- err_check_propagate(retval);
-
- uint32_t drscan_data;
- uint16_t tmp = (buffer[0]|(buffer[1]<<8));
- retval = core_tx_upper_data(target,tmp,&drscan_data);
- err_check_propagate(retval);
-
- retval = dsp5680xx_resume(target,0,my_favourite_ram_address,0,0);
- err_check_propagate(retval);
-
- int counter = FLUSH_COUNT_FLASH;
- dsp5680xx_context.flush = 0;
- uint32_t i;
- for(i=1; (i<count/2)&&(i<HFM_SIZE_WORDS); i++){
- if(--counter==0){
- dsp5680xx_context.flush = 1;
- counter = FLUSH_COUNT_FLASH;
- }
- tmp = (buffer[2*i]|(buffer[2*i+1]<<8));
- retval = core_tx_upper_data(target,tmp,&drscan_data);
- if(retval!=ERROR_OK){
- dsp5680xx_context.flush = 1;
- err_check_propagate(retval);
+ * r0: TX/RX high address.
+ * r2: FM module base address.
+ * r3: Destination address in flash.
+ *
+ * hfm_wait: // wait for buffer empty
+ * brclr #0x80, x:(r2+0x13), hfm_wait
+ * rx_check: // wait for input buffer full
+ * brclr #0x01, x:(r0-2), rx_check
+ * move.w x:(r0), y0 // read from Rx buffer
+ * move.w y0, p:(r3)+
+ * move.w #0x20, x:(r2+0x14) // write PGM command
+ * move.w #0x80, x:(r2+0x13) // start the command
+ * move.w X:(R2+0x13), A // Read USTAT register
+ * brclr #0x20, A, accerr_check // protection violation check
+ * bfset #0x20, X:(R2+0x13) // clear pviol
+ * bra hfm_wait
+ * accerr_check:
+ * brclr #0x10, A, hfm_wait // access error check
+ * bfset #0x10, X:(R2+0x13) // clear accerr
+ * bra hfm_wait // loop
+ * 0x00000000 0x8A460013807D brclr #0x80, X:(R2+0x13),*+0
+ * 0x00000003 0xE700 nop
+ * 0x00000004 0xE700 nop
+ * 0x00000005 0x8A44FFFE017B brclr #1, X:(R0-2),*-2
+ * 0x00000008 0xE700 nop
+ * 0x00000009 0xF514 move.w X:(R0), Y0
+ * 0x0000000A 0x8563 move.w Y0, P:(R3)+
+ * 0x0000000B 0x864600200014 move.w #32, X:(R2+0x14)
+ * 0x0000000E 0x864600800013 move.w #128, X:(R2+0x13)
+ * 0x00000011 0xF0420013 move.w X:(R2+0x13), A
+ * 0x00000013 0x8B402004 brclr #0x20, A,*+6
+ * 0x00000015 0x824600130020 bfset #0x20, X:(R2+0x13)
+ * 0x00000018 0xA967 bra *-24
+ * 0x00000019 0x8B401065 brclr #0x10, A,*-25
+ * 0x0000001B 0x824600130010 bfset #0x10, X:(R2+0x13)
+ * 0x0000001E 0xA961 bra *-30
+ */
+
+static const uint16_t pgm_write_pflash[] = {
+ 0x8A46, 0x0013, 0x807D, 0xE700,
+ 0xE700, 0x8A44, 0xFFFE, 0x017B,
+ 0xE700, 0xF514, 0x8563, 0x8646,
+ 0x0020, 0x0014, 0x8646, 0x0080,
+ 0x0013, 0xF042, 0x0013, 0x8B40,
+ 0x2004, 0x8246, 0x0013, 0x0020,
+ 0xA967, 0x8B40, 0x1065, 0x8246,
+ 0x0013, 0x0010, 0xA961
+};
+
+static const uint32_t pgm_write_pflash_length = 31;
+
+int dsp5680xx_f_wr(struct target *t, const uint8_t *b, uint32_t a, uint32_t count,
+ int is_flash_lock)
+{
+ struct target *target = t;
+
+ uint32_t address = a;
+
+ const uint8_t *buffer = b;
+
+ int retval = ERROR_OK;
+
+ if (!dsp5680xx_context.debug_mode_enabled) {
+ retval = eonce_enter_debug_mode(target, NULL);
+ err_check_propagate(retval);
+ }
+ /*
+ * Download the pgm that flashes.
+ *
+ */
+ const uint32_t len = pgm_write_pflash_length;
+
+ uint32_t ram_addr = 0x8700;
+
+ /*
+ * This seems to be a safe address.
+ * This one is the one used by codewarrior in 56801x_flash.cfg
+ */
+ if (!is_flash_lock) {
+ retval =
+ dsp5680xx_write(target, ram_addr, 1, len * 2,
+ (uint8_t *) pgm_write_pflash);
+ err_check_propagate(retval);
+ retval = dsp5680xx_execute_queue();
+ err_check_propagate(retval);