-int cortex_m3_prepare_reset_halt(struct target_s *target)
-{
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
- u32 dcb_demcr, dcb_dhcsr;
-
- /* Enable debug requests */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
- if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN );
-
- /* Enter debug state on reset, cf. end_reset_event() */
- ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
-
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
- ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
- DEBUG("dcb_dhcsr 0x%x, dcb_demcr 0x%x, ", dcb_dhcsr, dcb_demcr);
-
- return ERROR_OK;
-}
-