+int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, int regnum)
+{
+ int retval;
+ uint32_t dcrdr;
+
+ /* because the DCB_DCRDR is used for the emulated dcc channel
+ * we gave to save/restore the DCB_DCRDR when used */
+
+ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum );
+
+ /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+
+ mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ return retval;
+}
+
+int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, int regnum)
+{
+ int retval;
+ uint32_t dcrdr;
+
+ /* because the DCB_DCRDR is used for the emulated dcc channel
+ * we gave to save/restore the DCB_DCRDR when used */
+
+ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+
+ /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
+
+ mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ return retval;
+}
+
+
+int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t mask_off)
+{
+ /* get pointers to arch-specific information */
+ armv7m_common_t *armv7m = target->arch_info;
+ cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+
+ /* mask off status bits */
+ cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
+ /* create new register mask */
+ cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
+
+ return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
+}
+